iverilog-devel — Conversations on matters of Icarus Verilog development

Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Douglas S. <dc...@tr...>]

Julian,

In the case you mention, the always block will finish the update due to 
a changing, and then activate again because b changed. If we say that a 
changes from a0 to a1, and b changes from b0 to b1, then c will change 
from a0 & b0 to a1 & b0, and then to a1 & b1.

And since it could have updated b before the assignment to temp, it 
could have gone from a0 & b0 directly to a1 & b1. Since you are not 
specifying any delays here, I assume that a and b are changing "at the 
same time" (but not the same simulator cycle), so of course b could be 
the one to trigger the always block, giving a different intermediate 
state for c.

I remember someone saying "Time is natures way of ensuring that 
everything doesn't happen all at once." In verilog, time is the only way 
to ensure sequencing of signals: you can't assume the order of signals 
changing at the same time, and verilog will remain at that time 
(re-triggering any always blocks, gates, assign statements ...) until no 
more events are scheduled for that time.

Doug Sojourner

On 05/16/20 13:55, Julian Thomas Parkin wrote:

This isn't an issue with iverilog, but I have a question about the
execution semantics of Verilog. There isn't much information online
and a lot of it points to this mailing list
(e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
so I'm hoping it's alright if I ask here.

In 1364-2005, section 11.4.2 includes the following sentence (which
is also present in SystemVerilog): "Another source of nondeterminism
is that statements without time-control constructs in behavioral
blocks do not have to be executed as one event."

As an example, it presents the following:

   assign p = q;
   initial begin
       q = 1;
       #1 q = 0;
       $display(p);
   end

The simulator is allowed to process the "q = 0" assignment, then
suspend execution in favour of updating p, and then display p as 0.

Does this also apply to the typical style of always process used
to express combinatorial circuits ?

For example, if someone were to implement an and gate using a
temporary variable:

   always @(a or b) begin
       temp = a & b;
       c = temp;
   end

Say a and b both have pending update events. Could the simulator
update a, see that the always has been activated, execute
"temp = a | b;", then suspend execution to update b ? At which
point the always block is not sensitive to changes because it is
still being executed, so it ends up missing the second update even
though b is in the sensitivity list.

Is this valid behavior according to the standard ? Or does
"statements without time-control constructs" apply to the
"begin end" block as a whole and prevent it from being executed as
multiple events because it does have a time-control ? If this is
valid, do iverilog or other simulators ever behave in this manner ?


Thanks,

-Julian


_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Cary R. <cy...@ya...>]

 
In a multi threaded simulator this is certainly possible unless it has created some kind of dependency graph. Most/maybe all single threaded simulators and icarus specifically will execute the currently running process until it reaches some kind of time statement (the @ in this code) before switching to the next process. The order of the processes running is not deterministic, though most simulators use a FIFO queue so there is some known determinism for a specific simulator.
It would require a well controlled seed for repeatability, but I always thought pulling a random element from the queue would over many regressions find most timing races that people code, but never get bitten by since their simulator has at least some determinism.
Cary
    On Saturday, May 16, 2020, 3:05:26 PM PDT, Julian Thomas Parkin <jtp...@uw...> wrote:  
 
 This isn't an issue with iverilog, but I have a question about the
execution semantics of Verilog. There isn't much information online
and a lot of it points to this mailing list
(e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
so I'm hoping it's alright if I ask here.

In 1364-2005, section 11.4.2 includes the following sentence (which
is also present in SystemVerilog): "Another source of nondeterminism
is that statements without time-control constructs in behavioral
blocks do not have to be executed as one event."

As an example, it presents the following:

  assign p = q;
  initial begin
      q = 1;
      #1 q = 0;
      $display(p);
  end

The simulator is allowed to process the "q = 0" assignment, then
suspend execution in favour of updating p, and then display p as 0.

Does this also apply to the typical style of always process used
to express combinatorial circuits ?

For example, if someone were to implement an and gate using a
temporary variable:

  always @(a or b) begin
      temp = a & b;
      c = temp;
  end

Say a and b both have pending update events. Could the simulator
update a, see that the always has been activated, execute
"temp = a | b;", then suspend execution to update b ? At which
point the always block is not sensitive to changes because it is
still being executed, so it ends up missing the second update even
though b is in the sensitivity list.

Is this valid behavior according to the standard ? Or does
"statements without time-control constructs" apply to the
"begin end" block as a whole and prevent it from being executed as
multiple events because it does have a time-control ? If this is
valid, do iverilog or other simulators ever behave in this manner ?


Thanks,

-Julian


_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
  

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Stephen W. <st...@ic...>]

Add a "-Wsafe-extensions" warning flag, and have that flag off/on by default?

On Sat, May 16, 2020 at 3:47 PM Cary R. via Iverilog-devel
<ive...@li...> wrote:
>
> I have subsequently checked and we match at least one of the big 3 for how @ is handled so that's not a bug, but this was more a question how do we want to handle extension in general. For example: binary ~& and ~| and the number of pullup/down ports. I assume we should as a minimum report these as extensions unless the user has deemed them acceptable.
>
> So I think we have the following choices and we need to decide which path to take:
>
> 1. Not allow extension by default, but they can be enabled either individually or globally. This gives the maximum portability, but we miss out on enhanced functionality if portability is not a concern.
>
> 2. Allow the extensions by default and generate compile time warnings unless the warning is disabled either individually or globally. Do we also need a flag to disable extensions? I assume this would just turn the portability warnings into errors.
>
> My personal preference is for #2 with the ability to disable extensions when portability is needed. Also if #2 is implemented getting #1 is just flipping the default setting of the global disable flag which would make changing our mind in the future trivial. Does anyone else have an idea how we should handle this? I think getting this designed well in the beginning is important.
>
> Cary
>
>
> On Saturday, May 16, 2020, 2:53:24 PM PDT, Stephen Williams <st...@ic...> wrote:
>
>
> It makes sense to be strict about the syntax. There are likely lots of
> people who learn Verilog syntax from Icarus Verilog behaviors.
>
> The "@ *" vs. "@*" might be construed as an actual bug. If that's the
> case, then I would suggest NOT accepting the extended version, even in
> a generous mode. However, you are really going to have to convince me
> that @* is a single token. Pretty sure that is not the case. The
> standard has in the beginning an exhaustive list of all the lexical
> tokens, and @* is not listed there. Also, consider that @* and @(*)
> are specifically called out as valid.
>
> On Mon, May 11, 2020 at 12:38 AM Cary R. via Iverilog-devel
> <ive...@li...> wrote:
> >
> > I have found a couple things that could be considered enhancements, but are clearly not supported by the standard. My question is should we have these enhancements controlled by a flag of some sort so people can restrict Icarus to only accept what is supported by the standard? For example pullup/pulldown should only support a single port. @* is really a single token and the binary ~& and ~| are not in the standard. There may be more. Is some new strict flag the correct thing for this? I think @* not being a single token is a bug and probably should be fixed. I'm personally of the opinion only standard/commonly supported functionality should be enabled by default and an extension flag should be used to enable the rest of this if it is kept.
> >
> > This would likely require reworking some of the tests to pull out the enhancements to have them be in a separate file.
> >
> > Thoughts?
> >
> > Cary
> > _______________________________________________
> > Iverilog-devel mailing list
> > Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> st...@ic...              But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
>
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel



-- 
Steve Williams                "The woods are lovely, dark and deep.
st...@ic...              But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Re: [Iverilog-devel] Verilog execution of always block as multiple events

[Stephen W. <st...@ic...>]

This is an interesting problem, and has come down to an unwritten rule
that sequential statements are executed without interruption until
they voluntarily yield by a time or event statement. Many people who
tried to implement multi-threaded Verilog simulators have discovered
this assumption the hard way. The problem is that Verilog has no
thread synchronization primitives other than the time and event
controls, and so every Verilog programmer has used these controls
exactly that way. So:

always @(a or b) begin
  temp = a & b;
  c = temp;
end

Once this thread is started, it will run, uninterrupted, until it gets
to the @(...) statement, which yields the CPU.

Now, it can also be pointed out that this is technically only a single
statement. The @(a or b)... is a single statement that has as a
sub-statement a begin..end block. People don't usually think about it
that way, but it is technically true.

On Sat, May 16, 2020 at 3:05 PM Julian Thomas Parkin
<jtp...@uw...> wrote:
>
> This isn't an issue with iverilog, but I have a question about the
> execution semantics of Verilog. There isn't much information online
> and a lot of it points to this mailing list
> (e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
> so I'm hoping it's alright if I ask here.
>
> In 1364-2005, section 11.4.2 includes the following sentence (which
> is also present in SystemVerilog): "Another source of nondeterminism
> is that statements without time-control constructs in behavioral
> blocks do not have to be executed as one event."
>
> As an example, it presents the following:
>
>   assign p = q;
>   initial begin
>       q = 1;
>       #1 q = 0;
>       $display(p);
>   end
>
> The simulator is allowed to process the "q = 0" assignment, then
> suspend execution in favour of updating p, and then display p as 0.
>
> Does this also apply to the typical style of always process used
> to express combinatorial circuits ?
>
> For example, if someone were to implement an and gate using a
> temporary variable:
>
>   always @(a or b) begin
>       temp = a & b;
>       c = temp;
>   end
>
> Say a and b both have pending update events. Could the simulator
> update a, see that the always has been activated, execute
> "temp = a | b;", then suspend execution to update b ? At which
> point the always block is not sensitive to changes because it is
> still being executed, so it ends up missing the second update even
> though b is in the sensitivity list.
>
> Is this valid behavior according to the standard ? Or does
> "statements without time-control constructs" apply to the
> "begin end" block as a whole and prevent it from being executed as
> multiple events because it does have a time-control ? If this is
> valid, do iverilog or other simulators ever behave in this manner ?
>
>
> Thanks,
>
> -Julian
>
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel



-- 
Steve Williams                "The woods are lovely, dark and deep.
st...@ic...              But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Cary R. <cy...@ya...>]

 I have subsequently checked and we match at least one of the big 3 for how @ is handled so that's not a bug, but this was more a question how do we want to handle extension in general. For example: binary ~& and ~| and the number of pullup/down ports. I assume we should as a minimum report these as extensions unless the user has deemed them acceptable.
So I think we have the following choices and we need to decide which path to take:
1. Not allow extension by default, but they can be enabled either individually or globally. This gives the maximum portability, but we miss out on enhanced functionality if portability is not a concern.

2. Allow the extensions by default and generate compile time warnings unless the warning is disabled either individually or globally. Do we also need a flag to disable extensions? I assume this would just turn the portability warnings into errors.
My personal preference is for #2 with the ability to disable extensions when portability is needed. Also if #2 is implemented getting #1 is just flipping the default setting of the global disable flag which would make changing our mind in the future trivial. Does anyone else have an idea how we should handle this? I think getting this designed well in the beginning is important.

Cary


    On Saturday, May 16, 2020, 2:53:24 PM PDT, Stephen Williams <st...@ic...> wrote:  
 
 It makes sense to be strict about the syntax. There are likely lots of
people who learn Verilog syntax from Icarus Verilog behaviors.

The "@ *" vs. "@*" might be construed as an actual bug. If that's the
case, then I would suggest NOT accepting the extended version, even in
a generous mode. However, you are really going to have to convince me
that @* is a single token. Pretty sure that is not the case. The
standard has in the beginning an exhaustive list of all the lexical
tokens, and @* is not listed there. Also, consider that @* and @(*)
are specifically called out as valid.

On Mon, May 11, 2020 at 12:38 AM Cary R. via Iverilog-devel
<ive...@li...> wrote:
>
> I have found a couple things that could be considered enhancements, but are clearly not supported by the standard. My question is should we have these enhancements controlled by a flag of some sort so people can restrict Icarus to only accept what is supported by the standard? For example pullup/pulldown should only support a single port. @* is really a single token and the binary ~& and ~| are not in the standard. There may be more. Is some new strict flag the correct thing for this? I think @* not being a single token is a bug and probably should be fixed. I'm personally of the opinion only standard/commonly supported functionality should be enabled by default and an extension flag should be used to enable the rest of this if it is kept.
>
> This would likely require reworking some of the tests to pull out the enhancements to have them be in a separate file.
>
> Thoughts?
>
> Cary
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel



-- 
Steve Williams                "The woods are lovely, dark and deep.
st...@ic...              But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
  

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Stephen W. <st...@ic...>]

It makes sense to be strict about the syntax. There are likely lots of
people who learn Verilog syntax from Icarus Verilog behaviors.

The "@ *" vs. "@*" might be construed as an actual bug. If that's the
case, then I would suggest NOT accepting the extended version, even in
a generous mode. However, you are really going to have to convince me
that @* is a single token. Pretty sure that is not the case. The
standard has in the beginning an exhaustive list of all the lexical
tokens, and @* is not listed there. Also, consider that @* and @(*)
are specifically called out as valid.

On Mon, May 11, 2020 at 12:38 AM Cary R. via Iverilog-devel
<ive...@li...> wrote:
>
> I have found a couple things that could be considered enhancements, but are clearly not supported by the standard. My question is should we have these enhancements controlled by a flag of some sort so people can restrict Icarus to only accept what is supported by the standard? For example pullup/pulldown should only support a single port. @* is really a single token and the binary ~& and ~| are not in the standard. There may be more. Is some new strict flag the correct thing for this? I think @* not being a single token is a bug and probably should be fixed. I'm personally of the opinion only standard/commonly supported functionality should be enabled by default and an extension flag should be used to enable the rest of this if it is kept.
>
> This would likely require reworking some of the tests to pull out the enhancements to have them be in a separate file.
>
> Thoughts?
>
> Cary
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel



-- 
Steve Williams                "The woods are lovely, dark and deep.
st...@ic...              But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

[Iverilog-devel] Verilog execution of always block as multiple events

[Julian T. P. <jtp...@uw...>]

This isn't an issue with iverilog, but I have a question about the
execution semantics of Verilog. There isn't much information online
and a lot of it points to this mailing list
(e.g. https://sourceforge.net/p/iverilog/mailman/message/36358575/)
so I'm hoping it's alright if I ask here.

In 1364-2005, section 11.4.2 includes the following sentence (which
is also present in SystemVerilog): "Another source of nondeterminism
is that statements without time-control constructs in behavioral
blocks do not have to be executed as one event."

As an example, it presents the following:

  assign p = q;
  initial begin
      q = 1;
      #1 q = 0;
      $display(p);
  end

The simulator is allowed to process the "q = 0" assignment, then
suspend execution in favour of updating p, and then display p as 0.

Does this also apply to the typical style of always process used
to express combinatorial circuits ?

For example, if someone were to implement an and gate using a
temporary variable:

  always @(a or b) begin
      temp = a & b;
      c = temp;
  end

Say a and b both have pending update events. Could the simulator
update a, see that the always has been activated, execute
"temp = a | b;", then suspend execution to update b ? At which
point the always block is not sensitive to changes because it is
still being executed, so it ends up missing the second update even
though b is in the sensitivity list.

Is this valid behavior according to the standard ? Or does
"statements without time-control constructs" apply to the
"begin end" block as a whole and prevent it from being executed as
multiple events because it does have a time-control ? If this is
valid, do iverilog or other simulators ever behave in this manner ?


Thanks,

-Julian

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Michael S. <mic...@gm...>]

I agree. The extensions should be disabled by default to allow
interoperability between simulators.

Best regards,
Michael Strelnikov


On Mon, 11 May 2020 at 19:00, Martin Whitaker <ic...@ma...>
wrote:

> We have a bunch of extensions documented in the extensions.txt file and
> more documented in
>
> https://iverilog.fandom.com/wiki/Verilog_Portability_Notes
>
> We have compiler flags to control some but not all of these, but I agree
> an overarching flag would be a good idea. I would also be happy for
> extensions to be disabled by default.
>
> Tests that require Icarus extensions are meant to be kept separate in
> the test suite by the regress-ivl1.list and regress-ivl2.list, but it's
> been a while since I verified the test suite against another simulator,
> so there may be some escapes in more recent tests.
>
> On 11/05/2020 08:38, Cary R. via Iverilog-devel wrote:
> > I have found a couple things that could be considered enhancements, but
> are clearly not supported by the standard. My question is should we have
> these enhancements controlled by a flag of some sort so people can restrict
> Icarus to only accept what is supported by the standard? For example
> pullup/pulldown should only support a single port. @* is really a single
> token and the binary ~& and ~| are not in the standard. There may be more.
> Is some new strict flag the correct thing for this? I think @* not being a
> single token is a bug and probably should be fixed. I'm personally of the
> opinion only standard/commonly supported functionality should be enabled by
> default and an extension flag should be used to enable the rest of this if
> it is kept.
> >
> > This would likely require reworking some of the tests to pull out the
> enhancements to have them be in a separate file.
> > Thoughts?
>
>
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Martin W. <ic...@ma...>]

We have a bunch of extensions documented in the extensions.txt file and 
more documented in

https://iverilog.fandom.com/wiki/Verilog_Portability_Notes

We have compiler flags to control some but not all of these, but I agree 
an overarching flag would be a good idea. I would also be happy for 
extensions to be disabled by default.

Tests that require Icarus extensions are meant to be kept separate in 
the test suite by the regress-ivl1.list and regress-ivl2.list, but it's 
been a while since I verified the test suite against another simulator, 
so there may be some escapes in more recent tests.

On 11/05/2020 08:38, Cary R. via Iverilog-devel wrote:
> I have found a couple things that could be considered enhancements, but are clearly not supported by the standard. My question is should we have these enhancements controlled by a flag of some sort so people can restrict Icarus to only accept what is supported by the standard? For example pullup/pulldown should only support a single port. @* is really a single token and the binary ~& and ~| are not in the standard. There may be more. Is some new strict flag the correct thing for this? I think @* not being a single token is a bug and probably should be fixed. I'm personally of the opinion only standard/commonly supported functionality should be enabled by default and an extension flag should be used to enable the rest of this if it is kept.
> 
> This would likely require reworking some of the tests to pull out the enhancements to have them be in a separate file.
> Thoughts?

Re: [Iverilog-devel] bugs/enhancements in iverilog

[Jeremy B. <jer...@em...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 11/05/2020 08:38, Cary R. via Iverilog-devel wrote:
> I have found a couple things that could be considered enhancements,
> but are clearly not supported by the standard. My question is
> should we have these enhancements controlled by a flag of some sort
> so people can restrict Icarus to only accept what is supported by
> the standard? For example pullup/pulldown should only support a
> single port. @* is really a single token and the binary ~& and ~|
> are not in the standard. There may be more. Is some new strict flag
> the correct thing for this? I think @* not being a single token is
> a bug and probably should be fixed. I'm personally of the opinion
> only standard/commonly supported functionality should be enabled by
> default and an extension flag should be used to enable the rest of
> this if it is kept.

Hi Cary,

An important role of free and open source tools is to drive standards,
by providing a forum within which new ideas can be tested. Just look
at how C and C++ standards emerge from experimental work in GCC and
Clang/LLVM.

So I should strongly encourage you down this route, with suitable
flags to deal with standards enforcement.

It might be worth reaching out to over free and open source tools in
the space (for example Verilator) to agree some consistency over the
flags. And indeed to build consensus by providing support across a
range of tools.

HTH,


Jeremy

> This would likely require reworking some of the tests to pull out
> the enhancements to have them be in a separate file.
>
> Thoughts?
>
> Cary
>
>
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>


- -- 
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Twitter: @jeremypbennett
Email: jer...@em...
Web: www.embecosm.com
PGP key: 1024D/BEF58172FB4754E1 2009-03-20
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[Iverilog-devel] bugs/enhancements in iverilog

[Cary R. <cy...@ya...>]

I have found a couple things that could be considered enhancements, but are clearly not supported by the standard. My question is should we have these enhancements controlled by a flag of some sort so people can restrict Icarus to only accept what is supported by the standard? For example pullup/pulldown should only support a single port. @* is really a single token and the binary ~& and ~| are not in the standard. There may be more. Is some new strict flag the correct thing for this? I think @* not being a single token is a bug and probably should be fixed. I'm personally of the opinion only standard/commonly supported functionality should be enabled by default and an extension flag should be used to enable the rest of this if it is kept.

This would likely require reworking some of the tests to pull out the enhancements to have them be in a separate file.
Thoughts?
Cary

[Iverilog-devel] Maia verification language

[Evan L. <sa2...@cy...>]

You might be interested to see http://www.maia-eda.net: it's a
verification language, with a free download, and the compiler produces
Verilog output which runs on Icarus (and other sims, of course). I've
been developing it for some years and it has been used on various
projects I've been on, but this is the first public non-beta. The
website is a couple of days old so may be a little flakey, and I'm still
adding stuff.

When running chip regression and unit tests (which don't need a GUI, of
course) v10 is as good as the commercial sims I use. Maia's Verilog
output is V-2005, with no SV requirement, and v10's Verilog compliance
is good - it runs all the compiler test regressions without error (which
isn't true of all the commercial sims). Thanks for all the hard work!

[Iverilog-devel] state of VHDL (mixed-language) support

[Bryan M. <br...@ms...>]

I did a little internet searching to try to find out the current state 
of VHDL (mixed-language) support in iverilog is.  It sounds like there 
is interest and some work going on.  I'm interested in helping out with 
that.  Any pointers on where I can start?

Bryan
https://msd.llc/

Re: [Iverilog-devel] Fwd: Support for experimental logic states

[Cary R. <cy...@ya...>]

 Hi Daniel,
Could you describe what you are trying to do in a bit more detail? For example what is X polarity and how do you want to use it?

Conceptually adding new logical states is possible and could likely be done in a manner that would be mostly transparent to existing functionality.

Also if you are interested in efficient logic functionality, way too long ago I started experimenting with creating a general purpose library that supports all the Verilog operators for either 2 or 4 state logic. Unfortunately I have had no time to work on it for years though it has a bunch of functionality completed and I have many more ideas floating around in my brain regarding how it could be added to Icarus.

Knowing what you are trying to do in more detail should allow us to understand and better describe how Icarus could be used to satisfy your goals.

    On Thursday, February 13, 2020, 4:26:39 PM PST, Martin Whitaker <ic...@ma...> wrote:  
 
 Bryan Murdock wrote:
> Just so you know, Icarus can convert Verilog to VHDL, in case that helps.

The VHDL target is fairly limited in what it supports, and hasn't been 
maintained for many years, so I wouldn't recommend it.


_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
  

Re: [Iverilog-devel] Fwd: Support for experimental logic states

[Martin W. <ic...@ma...>]

Bryan Murdock wrote:
> Just so you know, Icarus can convert Verilog to VHDL, in case that helps.

The VHDL target is fairly limited in what it supports, and hasn't been 
maintained for many years, so I wouldn't recommend it.

Re: [Iverilog-devel] Fwd: Support for experimental logic states

[Bryan M. <bmu...@gm...>]

Just so you know, Icarus can convert Verilog to VHDL, in case that helps.

Bryan

On Thu, Feb 13, 2020, 5:19 AM Daniel Limbrick <dan...@nc...>
wrote:

> Thank you all for the feedback. Indeed, I was looking at the wrong GHDL
> page. I will test out a VHDL implementation of my circuits using GHDL (and
> vsim) to see if I can get the same performance improvement for don't care
> simulation that I noticed using Verilog in vsim. My guess is that the
> performance improvement is internal to vsim (don't care logic is optimized
> to shut off parts of the circuit and speed up computation), in which case,
> VHDL should produce the same results. My goal was to eventually be able to
> replicate this optimization in an open-source simulator. When I complete
> the tests, I will post the comparison to the forum. Thanks.
>
> Daniel
>
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc...
> Web page: http://daniellimbrick.com
>
>
> On Wed, Feb 12, 2020 at 1:49 PM Bryan Murdock <bryan@msd.llc> wrote:
>
>> Hi Daniel,
>>
>> I just wanted to confirm that GHDL is very active. The latest release
>> was about a year ago, and the next yearly release is being talked about
>> on github right now:
>>
>>
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fghdl%2Fghdl%2Fissues%2F1108&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=EA8dPg9kfdsUUD7KzjWaykpyOXPpFMrdt8nnL3KEQAE%3D&amp;reserved=0
>>
>> Also, Icarus can generate VHDL from Verilog if you have some existing
>> code that you need to convert over for this experiment.
>>
>> Bryan
>>
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmsd.llc%2F&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=lFqZ50M0xUIsxg3X1wbadmYYwmsc1a9wxl0MsB6nTlI%3D&amp;reserved=0
>>
>> On 2/12/20 11:40 AM, Bryan Murdock wrote:
>> >
>> >
>> > ---------- Forwarded message ---------
>> > From: *Daniel Limbrick* <dan...@nc...
>> > <mailto:dan...@nc...>>
>> > Date: Wed, Feb 12, 2020 at 8:48 AM
>> > Subject: Re: [Iverilog-devel] Support for experimental logic states
>> > To: Discussions concerning Icarus Verilog development
>> > <ive...@li...
>> > <mailto:ive...@li...>>
>> >
>> >
>> > Thanks for the response, Evan.
>> >
>> > Could you elaborate on how it would be trivial in VHDL? Do you mean
>> this
>> > type already exists or can be easily modified, e.g., something similar
>> > to std_ulogic? Or are you saying it is trivial to create, e.g.,
>> > importing a package that defines this type with the appropriate
>> > resolution table?
>> >
>> > My preference for Verilog comes from the availability of a mature
>> > open-source simulator. The only VHDL simulator I have seen/used is GHDL
>> > but I'm not sure development is active (hasn't been updated since
>> 2010).
>> > My goal is to maximize performance. I noticed that the Mentor Graphics
>> > tool vsim processes 'x' signals in Verilog faster than other signals. I
>> > wanted to study this effect and potentially use it.
>> >
>> > Regarding the delay in receiving my post, I am a new member so it may
>> > have taken time for me to get confirmed.
>> >
>> > Daniel
>> >
>> > --
>> > Daniel Limbrick, Ph.D.
>> > Associate Professor
>> > Electrical and Computer Engineering Department
>> > North Carolina A&T State University
>> > 523 McNair Hall
>> > Greensboro, NC 27411
>> > Office: 336-285-3310
>> > E-mail: dan...@nc... <mailto:dan...@nc...>
>> > Web page:
>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=qxS11W3guy5Avp1dzFHnrxPZDNjKwsFQDOuurDYN8EQ%3D&amp;reserved=0
>> >
>> >
>> > On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy...
>> > <mailto:sa212%2Bi...@cy...>> wrote:
>> >
>> >     Wouldn't this just be trivial with VHDL? Is there any particular
>> reason
>> >     to use Verilog?
>> >
>> >     Looks like your message took 6 days to get through to the list.
>> >
>> >     On 06/02/2020 17:44, Daniel Limbrick wrote:
>> >      > I am a researcher at North Carolina A&T State University working
>> on
>> >      > simulating faults in digital circuits. I am using your simulator
>> >     Icarus
>> >      > Verilog and I wanted to experiment with adding new states of
>> logic
>> >      > (beyond 0,1,x and z). I wanted to copy the specification for "x"
>> and
>> >      > create a version that keeps track of the polarity of "x".
>> >      >
>> >      > Do you have any documentation or notes that might help me
>> >     understand how
>> >      > to add this functionality? Also, is there an API for Icarus
>> >     extensions?
>> >      > Any help would be greatly appreciated. Thanks.
>> >      >
>> >      > Daniel
>> >      >
>> >      > --
>> >      > Daniel Limbrick, Ph.D.
>> >      > Associate Professor
>> >      > Electrical and Computer Engineering Department
>> >      > North Carolina A&T State University
>> >      > 523 McNair Hall
>> >      > Greensboro, NC 27411
>> >      > Office: 336-285-3310
>> >      > E-mail: dan...@nc...
>> >     <mailto:dan...@nc...> <mailto:dan...@nc...
>> >     <mailto:dan...@nc...>>
>> >      > Web page:
>> >
>> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=qxS11W3guy5Avp1dzFHnrxPZDNjKwsFQDOuurDYN8EQ%3D&amp;reserved=0
>> >      > ------- NOTICE: This e-mail correspondence is subject to Public
>> >     Records
>> >      > Law and may be disclosed to third parties. --------
>> >      >
>> >      >
>> >      > _______________________________________________
>> >      > Iverilog-devel mailing list
>> >      > Ive...@li...
>> >     <mailto:Ive...@li...>
>> >      >
>> >
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
>> >      >
>> >
>> >
>> >
>> >     _______________________________________________
>> >     Iverilog-devel mailing list
>> >     Ive...@li...
>> >     <mailto:Ive...@li...>
>> >
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
>> >
>> > ------- NOTICE: This e-mail correspondence is subject to Public Records
>> > Law and may be disclosed to third parties. --------
>> > _______________________________________________
>> > Iverilog-devel mailing list
>> > Ive...@li...
>> > <mailto:Ive...@li...>
>> >
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
>>
> ------- NOTICE: This e-mail correspondence is subject to Public Records
> Law and may be disclosed to third parties. --------
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] Fwd: Support for experimental logic states

[Daniel L. <dan...@nc...>]

Thank you all for the feedback. Indeed, I was looking at the wrong GHDL page. I will test out a VHDL implementation of my circuits using GHDL (and vsim) to see if I can get the same performance improvement for don't care simulation that I noticed using Verilog in vsim. My guess is that the performance improvement is internal to vsim (don't care logic is optimized to shut off parts of the circuit and speed up computation), in which case, VHDL should produce the same results. My goal was to eventually be able to replicate this optimization in an open-source simulator. When I complete the tests, I will post the comparison to the forum. Thanks.

Daniel

--
Daniel Limbrick, Ph.D.
Associate Professor
Electrical and Computer Engineering Department
North Carolina A&T State University
523 McNair Hall
Greensboro, NC 27411
Office: 336-285-3310
E-mail: dan...@nc...<mailto:dan...@nc...>
Web page: http://daniellimbrick.com


On Wed, Feb 12, 2020 at 1:49 PM Bryan Murdock <bryan@msd.llc> wrote:
Hi Daniel,

I just wanted to confirm that GHDL is very active. The latest release
was about a year ago, and the next yearly release is being talked about
on github right now:

https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fghdl%2Fghdl%2Fissues%2F1108&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=EA8dPg9kfdsUUD7KzjWaykpyOXPpFMrdt8nnL3KEQAE%3D&amp;reserved=0

Also, Icarus can generate VHDL from Verilog if you have some existing
code that you need to convert over for this experiment.

Bryan
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fmsd.llc%2F&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=lFqZ50M0xUIsxg3X1wbadmYYwmsc1a9wxl0MsB6nTlI%3D&amp;reserved=0

On 2/12/20 11:40 AM, Bryan Murdock wrote:
>
>
> ---------- Forwarded message ---------
> From: *Daniel Limbrick* <dan...@nc...<mailto:dan...@nc...>
> <mailto:dan...@nc...<mailto:dan...@nc...>>>
> Date: Wed, Feb 12, 2020 at 8:48 AM
> Subject: Re: [Iverilog-devel] Support for experimental logic states
> To: Discussions concerning Icarus Verilog development
> <ive...@li...<mailto:ive...@li...>
> <mailto:ive...@li...<mailto:ive...@li...>>>
>
>
> Thanks for the response, Evan.
>
> Could you elaborate on how it would be trivial in VHDL? Do you mean this
> type already exists or can be easily modified, e.g., something similar
> to std_ulogic? Or are you saying it is trivial to create, e.g.,
> importing a package that defines this type with the appropriate
> resolution table?
>
> My preference for Verilog comes from the availability of a mature
> open-source simulator. The only VHDL simulator I have seen/used is GHDL
> but I'm not sure development is active (hasn't been updated since 2010).
> My goal is to maximize performance. I noticed that the Mentor Graphics
> tool vsim processes 'x' signals in Verilog faster than other signals. I
> wanted to study this effect and potentially use it.
>
> Regarding the delay in receiving my post, I am a new member so it may
> have taken time for me to get confirmed.
>
> Daniel
>
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc...<mailto:dan...@nc...> <mailto:dan...@nc...<mailto:dan...@nc...>>
> Web page: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=qxS11W3guy5Avp1dzFHnrxPZDNjKwsFQDOuurDYN8EQ%3D&amp;reserved=0
>
>
> On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy...<mailto:sa212%2Bi...@cy...>
> <mailto:sa212%2Bi...@cy...<mailto:sa212%252...@cy...>>> wrote:
>
>     Wouldn't this just be trivial with VHDL? Is there any particular reason
>     to use Verilog?
>
>     Looks like your message took 6 days to get through to the list.
>
>     On 06/02/2020 17:44, Daniel Limbrick wrote:
>      > I am a researcher at North Carolina A&T State University working on
>      > simulating faults in digital circuits. I am using your simulator
>     Icarus
>      > Verilog and I wanted to experiment with adding new states of logic
>      > (beyond 0,1,x and z). I wanted to copy the specification for "x" and
>      > create a version that keeps track of the polarity of "x".
>      >
>      > Do you have any documentation or notes that might help me
>     understand how
>      > to add this functionality? Also, is there an API for Icarus
>     extensions?
>      > Any help would be greatly appreciated. Thanks.
>      >
>      > Daniel
>      >
>      > --
>      > Daniel Limbrick, Ph.D.
>      > Associate Professor
>      > Electrical and Computer Engineering Department
>      > North Carolina A&T State University
>      > 523 McNair Hall
>      > Greensboro, NC 27411
>      > Office: 336-285-3310
>      > E-mail: dan...@nc...<mailto:dan...@nc...>
>     <mailto:dan...@nc...<mailto:dan...@nc...>> <mailto:dan...@nc...<mailto:dan...@nc...>
>     <mailto:dan...@nc...<mailto:dan...@nc...>>>
>      > Web page:
>     https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092535849&amp;sdata=qxS11W3guy5Avp1dzFHnrxPZDNjKwsFQDOuurDYN8EQ%3D&amp;reserved=0
>      > ------- NOTICE: This e-mail correspondence is subject to Public
>     Records
>      > Law and may be disclosed to third parties. --------
>      >
>      >
>      > _______________________________________________
>      > Iverilog-devel mailing list
>      > Ive...@li...<mailto:Ive...@li...>
>     <mailto:Ive...@li...<mailto:Ive...@li...>>
>      >
>     https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
>      >
>
>
>
>     _______________________________________________
>     Iverilog-devel mailing list
>     Ive...@li...<mailto:Ive...@li...>
>     <mailto:Ive...@li...<mailto:Ive...@li...>>
>     https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
>
> ------- NOTICE: This e-mail correspondence is subject to Public Records
> Law and may be disclosed to third parties. --------
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...<mailto:Ive...@li...>
> <mailto:Ive...@li...<mailto:Ive...@li...>>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.sourceforge.net%2Flists%2Flistinfo%2Fiverilog-devel&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cf193a7599e6048e4647308d7b012628e%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637171466092545840&amp;sdata=fRHOUUIpEOJ2YudJSRFbNr6kl5s3urmRFjkKuy6p8Tw%3D&amp;reserved=0
------- NOTICE: This e-mail correspondence is subject to Public Records Law and may be disclosed to third parties. --------

Re: [Iverilog-devel] Fwd: Support for experimental logic states

[Bryan M. <br...@ms...>]

Hi Daniel,

I just wanted to confirm that GHDL is very active. The latest release 
was about a year ago, and the next yearly release is being talked about 
on github right now:

https://github.com/ghdl/ghdl/issues/1108

Also, Icarus can generate VHDL from Verilog if you have some existing 
code that you need to convert over for this experiment.

Bryan
https://msd.llc/

On 2/12/20 11:40 AM, Bryan Murdock wrote:
> 
> 
> ---------- Forwarded message ---------
> From: *Daniel Limbrick* <dan...@nc... 
> <mailto:dan...@nc...>>
> Date: Wed, Feb 12, 2020 at 8:48 AM
> Subject: Re: [Iverilog-devel] Support for experimental logic states
> To: Discussions concerning Icarus Verilog development 
> <ive...@li... 
> <mailto:ive...@li...>>
> 
> 
> Thanks for the response, Evan.
> 
> Could you elaborate on how it would be trivial in VHDL? Do you mean this 
> type already exists or can be easily modified, e.g., something similar 
> to std_ulogic? Or are you saying it is trivial to create, e.g., 
> importing a package that defines this type with the appropriate 
> resolution table?
> 
> My preference for Verilog comes from the availability of a mature 
> open-source simulator. The only VHDL simulator I have seen/used is GHDL 
> but I'm not sure development is active (hasn't been updated since 2010). 
> My goal is to maximize performance. I noticed that the Mentor Graphics 
> tool vsim processes 'x' signals in Verilog faster than other signals. I 
> wanted to study this effect and potentially use it.
> 
> Regarding the delay in receiving my post, I am a new member so it may 
> have taken time for me to get confirmed.
> 
> Daniel
> 
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc... <mailto:dan...@nc...>
> Web page: http://daniellimbrick.com
> 
> 
> On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy... 
> <mailto:sa212%2Bi...@cy...>> wrote:
> 
>     Wouldn't this just be trivial with VHDL? Is there any particular reason
>     to use Verilog?
> 
>     Looks like your message took 6 days to get through to the list.
> 
>     On 06/02/2020 17:44, Daniel Limbrick wrote:
>      > I am a researcher at North Carolina A&T State University working on
>      > simulating faults in digital circuits. I am using your simulator
>     Icarus
>      > Verilog and I wanted to experiment with adding new states of logic
>      > (beyond 0,1,x and z). I wanted to copy the specification for "x" and
>      > create a version that keeps track of the polarity of "x".
>      >
>      > Do you have any documentation or notes that might help me
>     understand how
>      > to add this functionality? Also, is there an API for Icarus
>     extensions?
>      > Any help would be greatly appreciated. Thanks.
>      >
>      > Daniel
>      >
>      > --
>      > Daniel Limbrick, Ph.D.
>      > Associate Professor
>      > Electrical and Computer Engineering Department
>      > North Carolina A&T State University
>      > 523 McNair Hall
>      > Greensboro, NC 27411
>      > Office: 336-285-3310
>      > E-mail: dan...@nc...
>     <mailto:dan...@nc...> <mailto:dan...@nc...
>     <mailto:dan...@nc...>>
>      > Web page:
>     https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&amp;sdata=PzGsR2%2BqXwULH%2FAORuM0DdcecbtfxmxsnTom3m%2Bz%2Fcg%3D&amp;reserved=0
>      > ------- NOTICE: This e-mail correspondence is subject to Public
>     Records
>      > Law and may be disclosed to third parties. --------
>      >
>      >
>      > _______________________________________________
>      > Iverilog-devel mailing list
>      > Ive...@li...
>     <mailto:Ive...@li...>
>      >
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Re: [Iverilog-devel] Support for experimental logic states

[Stefan D. <Dr...@ri...>]

I cannot help with your original question, but:

-        ghdl development is very active (last commit 11 hours ago on https://github.com/ghdl/ghdl) and the standard compliance is excellent (VHDL 2008 is still work in progress, but earlier standards are well supported)

-        if performance is your goal, then for VHDL ghdl should be your first choice, as it compiles the vhdl code to a native executable which makes simulation very fast (dumping VCD is a bottleneck though. Not sure whether you need this). For Verilog the project verilator does something similar and is also very fast.

From: Daniel Limbrick <dan...@nc...>
Sent: Wednesday, February 12, 2020 2:15 PM
To: Discussions concerning Icarus Verilog development <ive...@li...>
Subject: Re: [Iverilog-devel] Support for experimental logic states

Thanks for the response, Evan.

Could you elaborate on how it would be trivial in VHDL? Do you mean this type already exists or can be easily modified, e.g., something similar to std_ulogic? Or are you saying it is trivial to create, e.g., importing a package that defines this type with the appropriate resolution table?

My preference for Verilog comes from the availability of a mature open-source simulator. The only VHDL simulator I have seen/used is GHDL but I'm not sure development is active (hasn't been updated since 2010). My goal is to maximize performance. I noticed that the Mentor Graphics tool vsim processes 'x' signals in Verilog faster than other signals. I wanted to study this effect and potentially use it.

Regarding the delay in receiving my post, I am a new member so it may have taken time for me to get confirmed.

Daniel

--
Daniel Limbrick, Ph.D.
Associate Professor
Electrical and Computer Engineering Department
North Carolina A&T State University
523 McNair Hall
Greensboro, NC 27411
Office: 336-285-3310
E-mail: dan...@nc...<mailto:dan...@nc...>
Web page: http://daniellimbrick.com


On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy...<mailto:sa212%2Bi...@cy...>> wrote:
Wouldn't this just be trivial with VHDL? Is there any particular reason
to use Verilog?

Looks like your message took 6 days to get through to the list.

On 06/02/2020 17:44, Daniel Limbrick wrote:
> I am a researcher at North Carolina A&T State University working on
> simulating faults in digital circuits. I am using your simulator Icarus
> Verilog and I wanted to experiment with adding new states of logic
> (beyond 0,1,x and z). I wanted to copy the specification for "x" and
> create a version that keeps track of the polarity of "x".
>
> Do you have any documentation or notes that might help me understand how
> to add this functionality? Also, is there an API for Icarus extensions?
> Any help would be greatly appreciated. Thanks.
>
> Daniel
>
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc...<mailto:dan...@nc...> <mailto:dan...@nc...<mailto:dan...@nc...>>
> Web page: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&amp;sdata=PzGsR2%2BqXwULH%2FAORuM0DdcecbtfxmxsnTom3m%2Bz%2Fcg%3D&amp;reserved=0
> ------- NOTICE: This e-mail correspondence is subject to Public Records
> Law and may be disclosed to third parties. --------
>
>
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Re: [Iverilog-devel] Support for experimental logic states

[Evan L. <sa2...@cy...>]

> Could you elaborate on how it would be trivial in VHDL? Do you mean this 
> type already exists or can be easily modified, e.g., something similar 
> to std_ulogic? Or are you saying it is trivial to create, e.g., 
> importing a package that defines this type with the appropriate 
> resolution table?

I would just create the type (multi-value logic types are enumerated, 
and you just add your own). This is exactly what VHDL is for - not fast, 
but very flexible. The vendors all had their own incompatible MVL types 
in the early 80's, before std_logic_1164 came along, with a standardised 
9-value type (std_ulogic). I would just copy std_logic_1164 (lots of 
sources online) for your own 4-(or more-)value MVL, add a resolution 
function and some overloads, and you're done. The vendors will 
accelerate their own implementations of std_[u]logic, and you won't get 
that, of course.

> 
> My preference for Verilog comes from the availability of a mature 
> open-source simulator. The only VHDL simulator I have seen/used is GHDL 
> but I'm not sure development is active (hasn't been updated since 2010). 

You must be on the wrong website! GHDL is very active. I only use the 
commercial sims, though, so don't know anything about it.

> My goal is to maximize performance. I noticed that the Mentor Graphics 
> tool vsim processes 'x' signals in Verilog faster than other signals. I 
> wanted to study this effect and potentially use it.

I don't know about performance - any MVL is going to be relatively slow. 
Having said that, GHDL is probably fast (it has LLVM and GCC back-ends), 
and if it accelerates std_ulogic, maybe you could hack into that.

I don't think ModelSim's vsim is known for speed. They started out with 
VHDL, and I always got the impression that the later Verilog back-end 
was the same as the VHDL one, but it's just an impression.

Re: [Iverilog-devel] Support for experimental logic states

[Daniel L. <dan...@nc...>]

Thanks for the response, Evan.

Could you elaborate on how it would be trivial in VHDL? Do you mean this type already exists or can be easily modified, e.g., something similar to std_ulogic? Or are you saying it is trivial to create, e.g., importing a package that defines this type with the appropriate resolution table?

My preference for Verilog comes from the availability of a mature open-source simulator. The only VHDL simulator I have seen/used is GHDL but I'm not sure development is active (hasn't been updated since 2010). My goal is to maximize performance. I noticed that the Mentor Graphics tool vsim processes 'x' signals in Verilog faster than other signals. I wanted to study this effect and potentially use it.

Regarding the delay in receiving my post, I am a new member so it may have taken time for me to get confirmed.

Daniel

--
Daniel Limbrick, Ph.D.
Associate Professor
Electrical and Computer Engineering Department
North Carolina A&T State University
523 McNair Hall
Greensboro, NC 27411
Office: 336-285-3310
E-mail: dan...@nc...<mailto:dan...@nc...>
Web page: http://daniellimbrick.com


On Wed, Feb 12, 2020 at 4:54 AM Evan Lavelle <sa2...@cy...<mailto:sa212%2Bi...@cy...>> wrote:
Wouldn't this just be trivial with VHDL? Is there any particular reason
to use Verilog?

Looks like your message took 6 days to get through to the list.

On 06/02/2020 17:44, Daniel Limbrick wrote:
> I am a researcher at North Carolina A&T State University working on
> simulating faults in digital circuits. I am using your simulator Icarus
> Verilog and I wanted to experiment with adding new states of logic
> (beyond 0,1,x and z). I wanted to copy the specification for "x" and
> create a version that keeps track of the polarity of "x".
>
> Do you have any documentation or notes that might help me understand how
> to add this functionality? Also, is there an API for Icarus extensions?
> Any help would be greatly appreciated. Thanks.
>
> Daniel
>
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc...<mailto:dan...@nc...> <mailto:dan...@nc...<mailto:dan...@nc...>>
> Web page: https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdaniellimbrick.com&amp;data=02%7C01%7Cdblimbri%40ncat.edu%7Cc648539418484bfa34f608d7afa397dc%7Cd844dd75a4d74b1fbd33bc0b1c796c38%7C0%7C0%7C637170990069986489&amp;sdata=PzGsR2%2BqXwULH%2FAORuM0DdcecbtfxmxsnTom3m%2Bz%2Fcg%3D&amp;reserved=0
> ------- NOTICE: This e-mail correspondence is subject to Public Records
> Law and may be disclosed to third parties. --------
>
>
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Re: [Iverilog-devel] Support for experimental logic states

[Evan L. <sa2...@cy...>]

Wouldn't this just be trivial with VHDL? Is there any particular reason 
to use Verilog?

Looks like your message took 6 days to get through to the list.

On 06/02/2020 17:44, Daniel Limbrick wrote:
> I am a researcher at North Carolina A&T State University working on 
> simulating faults in digital circuits. I am using your simulator Icarus 
> Verilog and I wanted to experiment with adding new states of logic 
> (beyond 0,1,x and z). I wanted to copy the specification for "x" and 
> create a version that keeps track of the polarity of "x".
> 
> Do you have any documentation or notes that might help me understand how 
> to add this functionality? Also, is there an API for Icarus extensions? 
> Any help would be greatly appreciated. Thanks.
> 
> Daniel
> 
> --
> Daniel Limbrick, Ph.D.
> Associate Professor
> Electrical and Computer Engineering Department
> North Carolina A&T State University
> 523 McNair Hall
> Greensboro, NC 27411
> Office: 336-285-3310
> E-mail: dan...@nc... <mailto:dan...@nc...>
> Web page: http://daniellimbrick.com
> ------- NOTICE: This e-mail correspondence is subject to Public Records 
> Law and may be disclosed to third parties. --------
> 
> 
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

Re: [Iverilog-devel] maybe a silly question, but iverilog does not generate compile log file?

[fuyong <fuy...@gm...>]

thanks Martin.

On Fri, Feb 7, 2020 at 12:32 PM Martin Whitaker <
ic...@ma...> wrote:

> I'm not whether this is what you mean, but if running from bash or csh,
> something like this
>
>    iverilog -v test.v |& tee iverilog.log
>
> will capture all the output from stdout and stderr in iverilog.log.
>
> fuyong wrote:
> >>
> >> Thanks,
>
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] maybe a silly question, but iverilog does not generate compile log file?

[Martin W. <ic...@ma...>]

I'm not whether this is what you mean, but if running from bash or csh, 
something like this

   iverilog -v test.v |& tee iverilog.log

will capture all the output from stdout and stderr in iverilog.log.

fuyong wrote:
>>
>> Thanks,

[Iverilog-devel] Support for experimental logic states

[Daniel L. <dan...@nc...>]

I am a researcher at North Carolina A&T State University working on simulating faults in digital circuits. I am using your simulator Icarus Verilog and I wanted to experiment with adding new states of logic (beyond 0,1,x and z). I wanted to copy the specification for "x" and create a version that keeps track of the polarity of "x".

Do you have any documentation or notes that might help me understand how to add this functionality? Also, is there an API for Icarus extensions? Any help would be greatly appreciated. Thanks.

Daniel

--
Daniel Limbrick, Ph.D.
Associate Professor
Electrical and Computer Engineering Department
North Carolina A&T State University
523 McNair Hall
Greensboro, NC 27411
Office: 336-285-3310
E-mail: dan...@nc...<mailto:dan...@nc...>
Web page: http://daniellimbrick.com
------- NOTICE: This e-mail correspondence is subject to Public Records Law and may be disclosed to third parties. --------