#39 value list '{} support

[Iztok Jeras]

Hi,

SystemVerilog value list syntax '{} for writing to packed structures/arrays is not supported.

Some examples for this syntax are provided here: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/struct_packed_value_list.v && vvp a.out
iverilog -g2009 ivltests/array_packed_value_list.v && vvp a.out
or use attached files.

Regards,
Iztok Jeras

[Iztok Jeras]

example Verilog code (2 files)

[Iztok Jeras]

Hi,

The official name for this feature is "assignment patterns". In addition to structures/arrays it can also be used on 1D vectors.

An example for this syntax is provided here: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_assignment_pattern.v && vvp a.out
or use attached files.

Regards,
Iztok Jeras

[Iztok Jeras]

Hi,

The official name for this feature is "assignment patterns". In addition to structures/arrays it can also be used on 1D vectors.

An example for this syntax is provided here: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_assignment_pattern.v && vvp a.out
or use attached files.

Regards,
Iztok Jeras