Menu
▾
▴
#32 ifnone compiler error (no support for Cadence syntax)
I've tried to compile a verilog file, which contains a lot of CELL definitions (modules with specify construct). The file is the part of the library defined, supported and delivered by the well known foundry from Taiwan. The sample code (see the attachment test.v) is sanitized down to few offending verilog statements.
DESCRIPTION of the issue:
When I compile the test.v I get on the screen the following error message
Igor@ld112> iverilog test.v
test:v.15: syntax error
test:v.15: Invalid simple path
test:v.15: syntax error
test:v.11: error: syntax error in specify block
Compiling the same code with verilog-XL and ncverilog does NOT produce any warnings or errors.
I get the same error even if I compile the offending code with -g no-specify
igor@ld112> iverilog -g no-specify test.v
test.v:15: syntax error
test.v:15: Invalid simple path
test.v:15: syntax error
test.v:11: error: syntax error in specify block
I've searched the bug database and found there solved bugs related to ifnone.
All three test cases work flawlessly. These bugs are:
1877329
1877743
1700361
I've modified slightly the test case from the bug 1877329. It did not compile cleanly with verilog-XL and ncverilog. After the fix, all three compilers (iverilog,ncverilog and verilog-XL) were OK. The other two test cases from bugs 1877329 and 1700361 compile cleanly with all three compilers.
The working test case from the bug 1877743 follows.
module FULLADD (CO, S, A, B, CI);
input A;
input B;
input CI;
output CO;
output S;
wire CO_buff;
`ifdef WHATEVER
buf (CO, CO_buff);
`else
buf (CO, CO_buff);
`endif
// Some function
specify
// arc A --> CO
if (B === 1'b1 && CI === 1'b0) ( A => CO ) = (1,1);
if (B === 1'b0 && CI === 1'b1) ( A => CO ) = (1,1);
ifnone ( A => CO ) = (1,1);
endspecify
endmodule
================ version of the icarus verilog used =================
igor@ld112:> iverilog -v test.v
Icarus Verilog version 0.9.2 (v0_9_2)
Copyright 1998-2009 Stephen Williams
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
translate: /usr/local/lib/ivl/ivlpp -v -L -F"/tmp/ivrlg22bbc28fe" -f"/tmp/ivrlg2bbc28fe" -p"/tmp/ivrli2bbc28fe" | /usr/local/lib/ivl/ivl -v -C"/tmp/ivrlh2bbc28fe" -C"/usr/local/lib/ivl/vvp.conf" -- -
Icarus Verilog Preprocessor version 0.9.2 (v0_9_2)
Copyright (c) 1999-2009 Stephen Williams (steve@icarus.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
/usr/local/lib/ivl/system.sft: Processing System Function Table file.
/usr/local/lib/ivl/v2005_math.sft: Processing System Function Table file.
/usr/local/lib/ivl/va_math.sft: Processing System Function Table file.
Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc
PARSING INPUT
test.v:15: syntax error
test.v:15: Invalid simple path
test.v:15: syntax error
test.v:11: error: syntax error in specify block
This test case is OK with verilog-XL and ncverilog but not with iverilog
Fixing typo.
This
I've modified slightly the test case from the bug 1877329. It did not compile cleanly with verilog-XL and ncverilog. After the fix, all three compilers (iverilog,ncverilog and verilog-XL) were OK. The other two test cases from bugs 1877329 and 1700361 compile cleanly with all three compilers.
The working test case from the bug 1877743 follows.
should be changed to this
I've modified slightly the test case from the bug 1877329. It did not compile cleanly with verilog-XL and ncverilog. After the fix, all three compilers (iverilog,ncverilog and verilog-XL) were OK. The other two test cases from bugs 11877743 and 700361 compile cleanly with all three compilers.
https://sourceforge.net/tracker/index.php?func=detail&aid=1877329&group_id=149850&atid=775997
http://sourceforge.net/tracker/index.php?func=detail&aid=1877743&group_id=149850&atid=775997
http://sourceforge.net/tracker/index.php?func=detail&aid=1700361&group_id=149850&atid=775997
The working test case from the bug 1877329 follows.
This is likely a problem in the parser which is before the -g no-specify flag is used. I'll look at your proposed change for the pr1877743 test and the attached file some time tomorrow.
According to the standard (1364-2005) an ifnone only accepts a simple path and what the attached example is passing to it is an edge sensitive path. Given what ifnone is supposed to do it makes sense that it only supports a simple path. It looks like our friends from Taiwan are writing non-standard Verilog and unfortunately NC and XL accept this invalid syntax.
We could possibly add this functionality, but without an exact definition of how this is supposed to work we would likely get it wrong. If you can find documentation on how an ifnone with an edge sensitive path is supposed to work we may consider adding this, otherwise you need to get the library updated to use the correct syntax. It may be as simple as the edge sensitive stuff is ignored for an ifnone and the input and output are extracted to create a simple path for simulation. If this is the case then it's much better to just use the correct syntax and write this as a simple path so the reader of the code understands exactly what is going on.
I'm dropping the priority of this report to 5 and marking it as invalid, but I will leave it open for a while. I'll post a quick note to iverilog-devel to see what others think.
I've googled a little bit the net and confirmed your findings/description regarding ifnone and simple path. Even in a document from 1996 is the ifnone described in the similar way. http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf
BUT
at the same time I've found on the XILINX site http://www.xilinx.com/itp/xilinx7/help/iseguide/mergedProjects/hdledit/html/verilog_ifnone.htm
slightly different definition.
Verilog Reserved Word: ifnone
Purpose
The ifnone reserved word is used to specify a default state-dependent path delay when all other conditions for the path are false. The ifnone condition specifies the same module path source and destination as the state-dependent module paths. The following rules apply.
A) Only simple module paths may be described with the ifnone condition.
B) The state-dependent paths that correspond to the ifnone path may be either simple module paths or edge-sensitive paths.
C) If there are no corresponding state-dependent module paths to the ifnone module path, then the ifnone module path is treated the same as an unconditional module path.
D) It is illegal to specify both an ifnone condition for a module path, and an unconditional simple module path for the same module path.
Please pay attention to case B).
After this discovery (see B) I opened the library file from the well known Taiwanese foundry and checked where the offending ifnone statement is used. In other words, I've checked where exactly iverilog reports an error. The error is in ALL of the state dependent cells like DFF, SDFF, DLATCH etc.
So, it seems to me that ifnone should support edge-sensitive paths as well. It looks like that this is accepted by the industry, for example XILINX .
You are misinterpreting B. It says the paths that correspond to the ifnone may be either simple or edge-sensitive not that the ifnone path can be edge-sensitive. For this definition correspond means the other state-dependent delays that have the same input and output terminals as the ifnone.
FYI this text is basically straight from the standard.
Thanks for the clarification. It seems we are stuck. The odds are very low that the 'well known Taiwanese foundry' will change/modify their library file.
How we're not completely stuck is if other name brand simulators also cannot handle this syntax. At that point you can say the following name brand simulators do not support this invalid syntax, please update your library to use the correct syntax. We can even denote the exact sections in the standard that cover this and provide the correct syntax if that helps.
I have discovered that this is a documented Cadence deviation from the standard. I'll need to investigate what other tools do regarding this code. If we can determine exactly what Cadence does then we may be able to add support for this. I'm going to move this to the feature request tracker since this is a request to add a deviation/enhancement from the standard. It's not a bug in Icarus
I've submitted a patch for V0.9 as well as development that adds an error message when Icarus encounter an ifnone with an edge-sensitive path . This should be a bit more descriptive than the syntax errors it was producing before.
I have gate and SDF files for our latest circuits that is likely using a cell library from the same Taiwanese company. I will use these files when I have some free time to add support for this construct to the compiler and the SDF back annotation routine. The gate library also uses $countdrivers() which is a separate feature request, but the lines with $countdrivers() can be commented out without changing the normal library behavior. I'll look at adding support for everything, but $countdrivers() is a much lower priority than getting the edge sensitive ifnone working which has an effect on the circuit timing.
It also appears that conditional path delays are not supported in the SDF routine.
My running goal is to make Icarus work with my latest tape out (gate level with SDF annotation) once I've had some time to recover. This time it's going to be the Cadence style ifnone statements and any other required SDF improvements.
I'll formally take this when I start working on it.
Any progress for the missing functionality called 'ifnone' ? I am using the latest available Icarus Verilog version 0.9.6 (v0_9_6). The missing functionality is still missing. But, I am getting a lot better WARNING note "Sorry: ifnone with an edge-sensitive path is not supported."
EXAMPLE which fail:
ifnone (negedge CDN => (Q+:1'b0)) = (0, 0);
The verilog library file is written by the well known Taiwanese foundry
P.S.: verilog-XL (1995) and nc-verilog digest this construct without complaints.
Last edit: Igor 2013-06-03
Just so you know, this functionality will never be implemented in the V0.9 branch and it is also not part of the Verilog standard (it is a Cadence addition). If we don't have to implement/worry about the SDF back annotation then this would be easier to add. Enhancing SDF back annotation to work correctly for this and other constructs requires a major rework of the run time expression code. Since Icarus has known issues with specify blocks ans SDF support this specific report has been a low priority. If you can live without SDF support we may be able to add this functionality in a more timely manner.