#994 Internal error synthesizing mux

[Larry Doolittle]

$ iverilog -V | grep "version 1"
Icarus Verilog version 11.0 (devel) (s20150603-96-g19009ec)
Icarus Verilog Preprocessor version 11.0 (devel) (s20150603-96-g19009ec)
Icarus Verilog Parser/Elaborator version 11.0 (devel) (s20150603-96-g19009ec)
$ iverilog -Wall mismatch.v
$ iverilog -Wall mismatch.v -tsizer
mismatch.v:11: internal error: NetCondit::synth_async: Mux input sizes do not match. A size=17, B size=16
mismatch.v:11:               : asig node pins:
        0 pin0 p (strong0 strong1): 0x28129c0 mismatch.wave
mismatch.v:11:               : if_ statement:
        {ind} <= +wave[16:0];
mismatch.v:11:               : bsig node pins:
    0 pin0 p (strong0 strong1): 0x2803f30 mismatch._s33
mismatch.v:11:               : else_ statement:
        {ind} <= 16'sd0;
mismatch.v:9: error: Unable to synthesize synchronous process.
mismatch.v:8: warning: Process not synthesized.
1 error(s) in post-elaboration processing.

[Martin Whitaker]

Fixed in both the master and v10 branches.