#987 vhdlpp won't accept null if-statement body

[Larry Doolittle]

As found in production VHDL code that synthesizes with Xilinx XST

$ iverilog -g2005-sv bug5.vhd 

bug5.vhd:17: syntax error

bug5.vhd:17: error: Too many errors in sequence within if_statement.

Encountered 2 errors parsing bug5.vhd

No top level modules, and no -s option.

Test case compiles fine if the statement in the if body is un-commented

[Stephen Williams]

Fixed in git master.