#978 assertion involving addition of $ivlh_to_unsigned() result

[Larry Doolittle]

$ iverilog ccc.v
ccc.v:3: assert: expr_synth.cc:103: failed assertion expr_width() >= rsig->vector_width()
Aborted

This with git master as of 2015-05-21.
Test case derived from longer VHDL code, but this is purely on the Verilog side -- although $ivlh_to_unsigned() is listed as an Icarus-specific extension.

[Martin Whitaker]

The implementation of $ivlh_to_unsigned was based on $unsigned. Unlike $unsigned, $ivlh_to_unsigned has to handle a reduction in width.

I've pushed a fix for this to the master branch.