Icarus Verilog / Bugs / #972 iverilog assertion failure with combinational loop in module output signal

#972 iverilog assertion failure with combinational loop in module output signal

Milestone: devel

Status: closed-fixed

Owner: Martin Whitaker

Labels: None

Priority: 5

Updated: 2015-04-25

Created: 2015-04-23

Creator: Peter Johnson

Private: No

iverilog crashes with an assertion failure when I run the attached Verilog file. The module has a single input and output. The output assignment has itself on the right hand side of the assignment creating a combinational loop. Not exactly a desired behavior but iverilog should not crash with this construct. This occurs in a build that I just pulled from git.

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foo.v

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Martin Whitaker - 2015-04-25

assigned_to: Martin Whitaker
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Martin Whitaker - 2015-04-25

status: open --> closed-fixed
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Martin Whitaker - 2015-04-25

I've pushed a fix for this to both the development branch and the v0.9 branch.

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iverilog assertion failure with combinational loop in module output signal

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#972 iverilog assertion failure with combinational loop in module output signal

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