iverilog crashes on Windows 7 Home Premium 64-bit with the command given below and attached file(IdealMemory.v). Windows indicates that "ivl.exe has stopped working". Installed with iverilog-0.9.7_setup.
Command:
C:\Users\Austin\spring15\csce350\project2>iverilog IdealMemory.v
Assertion failed: number_is_immediate(rword_idx, IMM_WID, 0), file ../../verilog-0.9.7/tgt-vvp/vvp_process.c, line 1256
The command executes successfully after removing the assign keyword from line 22 in IdealMemory.v. The issue also appears to exist when iverilog is installed on Ubuntu 14.04 via apt-get:
$iverilog IdealMemory.v
ivl: vvp_process.c:1256: force_link_rval: Assertion `number_is_immediate(rword_idx, 32, 0)' failed.
This is also failing for the development branch so I'm switching this bug to development. It is unlikely this will be fixed in V0.9 unless it is a trivial fix that is easily back ported since we plan to release V10 fairly soon.
This is another manifestation of bug #605 - Icarus doesn't properly support variable expressions on the RHS of a procedural continuous assignment. I've converted the assert to a "sorry" message in the development branch.
With this fix, your code should now work. But you would get a better model of an asynchronous RAM (and avoid the "sorry" message) if you used a normal continuous assignment instead of a procedural one (think about what triggers re-evaluation of the assignment).
I've also added the "sorry" messages to the v0.9 branch.The underlying problem is covered by bug #605, so I'm going to close this as fixed.
Hi,
I am using Icarus Verilog version 0.9.7 (v097), and my operating system is Ubuntu 16.04. I am reading a 8 x 8 rgb (red - green - blue) bitmap image from a bin file and changing the colourspace to yCoCg (yellow - chromium orange - chromium green) using a fast adder that I named KoggeStone. The code reads the pixel values from a bin file and writes to another. Note that when I try to compile the code I get a similar error like Mr Garrard has reported. Strangely if I remove the assign keyword from line 31 the code works just fine. Please help me here.
Last edit: Arnab Sanyal 2016-10-11
Why do you even have the "assign" keyword there in the first place? It looks
to me like you are just using the for loop to collect the output and write
it to
an output file. The "assign" is not needed for that situation.
On Mon, Oct 10, 2016 at 5:44 PM, Arnab Sanyal lonewolf1898@users.sf.net
wrote:
--
Steve Williams "The woods are lovely, dark and deep.
steve@icarus.com steveicarus@gmail.com But I have promises
to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
Related
Bugs:
#971This is a different bug to the original report - a different assertion is failing. However, this bug is also fixed in the current release of Icarus Verilog (v10.1), which outputs a suitable error message instead. I would strongly recommend updating to the current release - v0.9 has many known bugs, and is no longer being maintained.
Note that a procedural continuous assignment to an array word is not legal Verilog (and questionably legal in SystemVerilog). But as Steve has said, for what you are trying to do, an ordinary procedural assignment (i.e removing the
assign
keyword) will suffice.