#942 VHDL function bodies in arch declaration not supported

[Olof Kindgren]

Code with function bodies in architecture declaration fails to compile. Function declaration is treated as a syntax error

library ieee;
use ieee.std_logic_1164.all;

entity e is
  port (
    clk : in  std_logic;
    rst : in  std_logic;
    q   : out std_logic);
end e;

architecture a of e is

  signal r : std_logic;

  function invert (
    i : std_logic)
    return std_logic is
  begin
    return not i;
  end invert;
begin

   q <= r;

   process(clk)
   begin
     if rising_edge(clk) then
       if rst = '1' then
         r <= '0';
       else
         r <= invert(r);
       end if;
     end if;
   end process;
end a;

[Olof Kindgren]

I did some happy hacking on lex/bison/yacc whatever sources and found that the following was missing. This doesn't do the whole job though.

diff --git a/vhdlpp/parse.y b/vhdlpp/parse.y
index 873d21e..83e0c2e 100644
--- a/vhdlpp/parse.y
+++ b/vhdlpp/parse.y
@@ -500,6 +500,8 @@ block_declarative_item

   | use_clause_lib

+  | subprogram_body
+
       /* Various error handling rules for block_declarative_item... */

   | K_signal error ';'

[Martin Whitaker]

This should get you the rest of the way:

diff --git a/vhdlpp/architec_emit.cc b/vhdlpp/architec_emit.cc
index b53f94a..20b00c2 100644
--- a/vhdlpp/architec_emit.cc
+++ b/vhdlpp/architec_emit.cc
@@ -97,6 +97,11 @@ int Architecture::emit(ostream&out, Entity*entity)
       errors += emit_signals(out, entity, this);
       errors += emit_variables(out, entity, this);

+      for (map<perm_string,Subprogram*>::const_iterator cur = cur_subprograms_.begin()
+                ; cur != cur_subprograms_.end() ; ++ cur) {
+           errors += cur->second->emit_package(out);
+      }
+
       for (list<Architecture::Statement*>::iterator cur = statements_.begin()
                 ; cur != statements_.end() ; ++cur) {

But expect to find many other things that are not yet implemented - VHDL support in Icarus is a work in progress, and not that high up the priority list.

N.B. If you want to see the intermediate Verilog produced by the VHDL pre-processor, you can just run it on its own, e.g.

/usr/local/lib/ivl/vhdlpp -w"ivl_vhdl_work" test.vhd

[Olof Kindgren]

Works like a charm. What's the preferred way of submitting patches btw? github pull requests, e-mailed diffs or something else? I'll try to summon patches for a few other issues as well when I have time

[Cary R.]

Most previous patches have been diff files generated using git format-patch. Steve may allow pull requests, but he will have to reply on that. If you submit a patch generated using git format-patch to our SourceForge patch tracker or attached it to the appropriate report here in the bug tracker either Martin or I can apply and push the patch to the master repository once we have reviewed it.

[Martin Whitaker]

No need to submit a patch for this particular bug, as I already have the changes in my local repository. I'll push them shortly, once I've written a regression test.

[Martin Whitaker]

I've pushed the fix for this and a regression test to github.

[Olof Kindgren]

This is unfortunately broken again in the master branch

[Cary R.]

We have added a test for this problem to the test suite and it is now working again and will be caught if we accidentally break it in the future.