The following test fails to compile due to attributes being treated as syntax errors
library ieee; use ieee.std_logic_1164.all; entity e is port ( clk : in std_logic; rst : in std_logic; q : out std_logic); end e; architecture a of e is signal r : std_logic; attribute syn_keep : boolean; attribute syn_keep of r : signal is true; begin q <= r; process(clk) begin if rising_edge(clk) then if rst = '1' then r <= '0'; else r <= not r; end if; end if; end process; end a;
WIP patch for this issue. Looking for a few pointers
1. Is there a preferred way to issue a warning that support is missing without aborting the parsing? sorrymsg looks like it stops the parser
2. Is it OK to cheat a bit and use IDENTIFIER instead of implementing all the sub rules, as attribute_{declaration,specification} are the only rules that use them anyway?
Here's a little philosophy regarding how messages should be tagged in Icarus.
Error is for a real syntax error and should eventually abort.
Sorry is for things that are not supported and may be required so they should also eventually abort.
Warning is to inform the user that something may not be correct but an appropriate default is available so it will be used and the compilation will not abort.
All these should display the file and line information if it is available.
So with what you have said these messages should probably be warnings and you can use cerr to display the message. See the Verilog compiler parse.y (in the top directory) for an example. For the entity specification can you use a list of identifiers to get the full behavior?
I don't know VHDL very well, but if attributes are not required to effect the simulation or be available using some interface during the simulation just ignoring them without a warning should be okay.
On 12/11/2013 04:12 PM, Cary R. wrote:
Warnings are only for things that are legal, but possibly wrong.
I think that's what you meant, but not quite what you said.
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