Icarus Verilog / Bugs / #858 VHDL signal initialization doesn't detect errors

#858 VHDL signal initialization doesn't detect errors

Milestone: devel

Status: open

Owner: nobody

Labels: Verilog compiler bug (683)

Priority: 4

Updated: 2012-12-10

Created: 2011-11-10

Creator: Stephen Williams

Private: No

In VHDL, signal initialization assignment requires that the expression be constant, so that it can be evaluated at compile time. Icarus Verilog is not generating an error here.

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Stephen Williams - 2011-11-10

Example of the (lack of) error.

signal_init_assign_ERROR.vhd

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VHDL signal initialization doesn't detect errors

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#858 VHDL signal initialization doesn't detect errors

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