#829 VVP error when trying to $dumpvars real array

[DDaly]

I am trying to view the value of a real array by using the approach described here:
http://iverilog.wikia.com/wiki/Verilog_Portability_Notes (dumping array words)

iVerilog successfully compiles the code, but when running vvp, I get the error:
VCD warning: array word ex.aaa[0] will conflict with an escaped identifier.
sorry: Format 1 not implemented for getting real values.
vvp: vpi_priv.cc:751: void vpip_real_get_value(double, s_vpi_value*): Assertion `0' failed.
Aborted

The code is as follows:

module ex();

reg real aaa [1:0];
reg real b;

initial begin
aaa[0] <= 0.333;
aaa[1] <= 0.12312;
b <= 0;

#100;
b <= aaa[0];
#100;

end

initial
begin
$dumpvars(0,aaa[0]);

end

endmodule

[Cary R.]

This is not a trivial item to fix. It requires enhancing the VPI interface and rewriting a fair number of the system tasks, etc.. The fundamental issue is that the VPI interface currently assumes that all arrays word are from vector based arrays and all array words even real ones are treated as array words. In reality array words are only for registers and the real variable type has the ability to act as an array.

You can work around this problem by using an escaped identifier for each array word you want to dump. Unfortunately you can't use the looping method to create them.

wire real \aaa_[0] = aaa[0];

and then $dumpvars(0, \aaa_[0] );

Don't forget the space after the escaped identifier. I add an underscore after the array name to make it unique.

FYI instead of writing reg real you should just write real since that is portable.