#630 Icarus Verilog accepts forward references too liberally

[Stephen Williams]

It turns out that many compilers do not accept forward references. Forware parameter references in particular are widely rejected by other compilers. Icarus Verilog should at least issue a warning for this:

module m;
parameter b = c+3; // illegal forward ref to 'c'
parameter c = 2;
reg a;
initial a = b;
endmodule

Forward references of variables need to also be checked with reality. There is evidence that Icarus Verilog is too liberal there as well.

I'm torn as to whether I should assign this to 0.9. I'm thinking not, as it would be easy to back-port a warning (as long as it is a warning, and not an error) from devel.