The -pdebug=1 switch is extremely helpful, many thanks for taking the time to implement it.
Icarus Verilog version 0.9.devel (s20080905-267-gfc00bd9)
$ iverilog -tvhdl test.v
assertion "decl" failed: file "stmt.cc", line 135
module test ();
reg [2:0] state;
reg [2:0] state_n;
reg CycleStarted;
function [2:0] Defaults;
input [2:0] curState;
begin
CycleStarted = 1'b0;
Defaults = curState;
end
endfunction
always @(state)
case(state)
0: begin
state_n = Defaults(state);
end
endcase
endmodule
This one appears to be the assignment to the global CycleStarted variable inside the function. I'll leave this one for Nick as well.
The problem here is that there's no way to assign to the non-local signal CycleStarted from inside a VHDL function (even if we declare it `impure' it can only read non-local signals). One way to do this might be to create a VHDL procedure instead and pass all the required signals in as inout parameters, but this is difficult since we potentially don't know about the non-local assignment until we're nearly done generating the function. Another solution might be to expand these functions inline, but this is still problematic since we have to determine which ones assign to non-local signals.
In the meantime I've made a few changes to the assignment generation code so we can now catch this case and output a useful error message rather than the unhelpful assertion failure.
I now get this when I run it:
nick@pickle:~/testsuite$ iverilog -tvhdl -o test.vhd test.v
VHDL conversion error: Unable to translate assignment at test.v:9
Translating this would require generating a non-blocking (<=)
assignment in a VHDL context where this is disallowed (e.g.
a function).
error: Code generation had 1 errors.
Might be a good idea dropping the priority down a bit, now that the compiler isn't actually crashing. I'll have to think about how we can work around this.
Nick's patch mentioned earlier is applied to git master.
I've changed the summary to make it a bit more meaningful when I look at the bug list :-)