Short code snippet can trigger an assert when using the vhdl target.
module bug_tvhdl;
wire signed [15:0] acc[0:3];
assign acc[0]=0;
endmodule
Tested with today's git master. Specifically:
ivl: tgt-vhdl/scope.cc:1087: int draw_constant_drivers(ivl_scope_t, void*): Assertion `j == 0' failed.
That line of c++ code is marked as "TODO: Make work for more words".
Unfortunately the VHDL target is currently unmaintained. I don't know enough VHDL to take that on.