#1031 Parameters defined in package not seen in Verilog module imported it

[Gil]

It seems like importing parameters from package in to the namespace of a module does not work.
This happens either when importing the entire package content or specified parameter name.
Compilation fails to bind the parameter unless it is explicitly redefined in the Verilog module.

Example code:

File: if_package.sv

package if_package;
parameter WIDTH=8;
typedef struct packed {
logic val;
logic [WIDTH-1:0] din;
} data_if ;
endpackage // if_package

File: package_test.sv
module package_test
import if_package::*;
(
input [WIDTH-1:0] opA,
input data_if c
);
initial begin
$display ("WIDTH:%0d c.val:%b c.din%x ",
WIDTH, c.val, c.din);
end
endmodule // package_test

Compilation result:

iverilog -g2012 if_package.sv package_test.sv
if_package.sv:7: error: Unable to bind parameter WIDTH' inpackage_test'
1 error(s) during elaboration.

Adding explicit parameter definition line to package_test.sv scope removes the error:

parameter WIDTH = if_package::WIDTH;

In other simulators importing package contents exposes its parameter namespace for the module, so there is no need to redifine. As the technique to define global parameter becomes common coding style, supportingthis would simplify porting source code to Icarus Verilog.

Regards,
Gil.

[Martin Whitaker]

This is now fixed in the master branch. The fix is unlikely to be backported to the v10 branch as it is the result of a significant rework of the parser.