#1027 v10 regression: task inout parameter copy-out fails, Ok in 0.9.7

[Evan Lavelle]

The attached test program passes on 0.9.7, but fails on current git (v10-branch, and the v0.10.0 at edaplayground.com). This is a very simple test that checks copy-out on a task inout parameter. This seems pretty fundamental, so I've set the priority high.

edaplayground.com confirms the expected result for Riviera, Incisive, and VCS; see the code for details. The output is

               0 a=001; b=010; c=011; d=100
               1 a=010; b=010; c=011; d=100
               2 a=010; b=010; c=100; d=100

See the attachment for the expected output.

Thank you.

[Martin Whitaker]

Confirmed it also fails on the master branch. This is yet more fallout from the SystemVerilog enhancements. The parser is applying the default port direction (input) to each port item that doesn't explicitly include a direction, whereas it should only use the default for the first item, then inherit from left to right.

Changing the task declaration to

task swap(inout reg[2:0] x, inout reg[2:0] y);

gives the correct output.

[Martin Whitaker]

I've pushed a fix for this to both the master and v10 branches on GitHub.

[Evan Lavelle]

Thank you - confirmed fixed.