#1024 SystemVerilog parameter arrays are not supported

[Shareef]

Hi there,

I'm trying to use parameter arrays in Verilog and Icarus is spitting out a compile error where Verilator, for example, is happy. I can't see in the Verilog LRM that there is support for arrays but I found a syntax example online that seems to work. So I'm not sure if this is a bug or if it's not supported.

Example uploaded.

$ iverilog ./test.v
./test.v:2: syntax error
./test.v:2: error: syntax error in parameter list.

Thanks, Shareef.

[Martin Whitaker]

Parameter arrays are a SystemVerilog feature. Currently Icarus only implements a subset of SystemVerilog and, sorry to say, this feature is not yet supported.