#1015 Declaring array ports for tasks/functions causes an assertion failure

[Sarma Vrudhula]

Assertion failed: (ivl_signal_dimensions(port) == 0), function function_argument_logic, file draw_ufunc.c, line 30.
sh: line 1: 38594 Done /usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/ivlpp -v -L -F"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlg226a91740" -f"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlg26a91740" -p"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrli26a91740"
38595 Abort trap: 6 | /usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/ivl -v -C"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlh26a91740" -C"/usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/vvp.conf" -- -

[Sarma Vrudhula]

sorry for the trouble. I'm new to verilog.

thanks
Sarma

On Sun, Jul 2, 2017 at 12:46 PM, Martin Whitaker martinwhitaker@users.sf.net wrote:

• summary: Assertion Failed --> Declaring array ports for
  tasks/functions causes an assertion failure
• Group: v10 --> devel
• Priority: 7 --> 5
• Comment:

This is happening because you have declared a function port as an array:

input Bits [NBits-1:0]

This is a SystemVerilog feature that is not currently supported by Icarus.
Of course the compiler should output a suitable error message rather than
an assertion failure. But in your case you don't need this functionality,
and can fix the problem by writing:

input [NBits-1:0] Bits

Reassigning to devel, as that's where this will be fixed first.

• [bugs:#1015] https://sourceforge.net/p/iverilog/bugs/1015/ Declaring
  array ports for tasks/functions causes an assertion failure*

Status: open
Group: devel
Labels: Assertion Failure
Created: Sun Jul 02, 2017 11:16 AM UTC by Sarma Vrudhula
Last Updated: Sun Jul 02, 2017 11:16 AM UTC
Owner: nobody
Attachments:

• SelfTimed_PNAND5_v2.v
  https://sourceforge.net/p/iverilog/bugs/1015/attachment/SelfTimed_PNAND5_v2.v
  (5.1 kB; application/octet-stream)

Assertion failed: (ivl_signal_dimensions(port) == 0), function
function_argument_logic, file draw_ufunc.c, line 30.
sh: line 1: 38594 Done /usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/ivlpp
-v -L -F"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlg226a91740"
-f"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlg26a91740"
-p"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrli26a91740"
38595 Abort trap: 6 | /usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/ivl
-v -C"/var/folders/4h/s3tn_h_s2ksgvx8t5lwz9wl00000gq/T//ivrlh26a91740"
-C"/usr/local/Cellar/icarus-verilog/10.1.1/lib/ivl/vvp.conf" -- -

---

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/iverilog/bugs/1015/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

[Martin Whitaker]

This is happening because you have declared a function port as an array:

input Bits [NBits-1:0]

This is a SystemVerilog feature that is not currently supported by Icarus. Of course the compiler should output a suitable error message rather than an assertion failure. But in your case you don't need this functionality, and can fix the problem by writing:

input [NBits-1:0] Bits

Reassigning to devel, as that's where this will be fixed first.

[Martin Whitaker]

Fixed in both master and v10 branches. If compiling with -g2005 or earlier, an error message will be output, otherwise a "sorry" message will be output to indicate this feature is not yet supported.