#1009 Parameter no set correctly

[Arie Peled]

As the number of bits of a is known at compile time i expected that the value of WIDTH will be 32 and not 0.

i usef the following command line with version 10.1 compiler:
iverilog test1.v

module test1();

reg [31:0] a;
parameter WIDTH=$bits(a);
reg [7:0] b;

initial
begin
b=$bits(a);

$display("a has %d bits,WIDTH=%d, b is %d",$bits(a),WIDTH,b);
$finish;
 end

endmodule

Actual output:

a has 32 bits,WIDTH= 0, b is 32

best regards,
Arie

[Martin Whitaker]

Setting priority to 7, as this is an incorrect result without any obvious workaround. But it's not obvious how to fix it. The problem is that parameters are evaluated early in the compilation, before the width of variables is calculated.

Setting the target to devel, as that's where it will be fixed first.