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#67 [req 155] Support for Bit endianness

Freescale
open
Register (18)
5
2011-03-31
2011-03-31
No

To represent the bit endianness of the register for example : register could be [31:0] or [0:31]

Discussion

  • martin baynes

    martin baynes - 2011-03-31
    • labels: --> Register
     
  • martin baynes

    martin baynes - 2011-03-31

    From clarification in requirements spreadsheet @ 3/3/2011
    "DUOLOG via martin: DEFER
    SNPS: Not supported by modelling languages
    AGNISYS: Register model in IP-XACT is not dependent on any particular modeling language."
    From clarification in RWG 3/31/2011 (from comments in the meeting)
    "Use of lsb0/msb0 is preferred to bit endianess.
    IP-XACt is lsb0 throughout.
    To add msb0 for registers would create a large amount of change and potential for confusion, whereas msb0 can be derived from lsb0 (and vice versa)
    It was agreed that annotation the IP-XACT in some way to show if the display should be lsb0 or msb0 (default lsb0) would be helpful."
    --> requirement could be restated "To capture the bitendianess (lsb0,msb0) intended in IP-XACT, while continuing to represet as lsb0 in IP-XACT"
    From Martin Baynes 3/31/2011
    "SystemRDL uses the notation msb0, lsb0 para 7.2 and defines which is the mode for a addressmap in para 10.3
    An addressmap in SystemRDL is also a leaf component in IP-XACT (see Para 9) - 'definines the RTL implementation boundary'
    --> the property to track lsb0,msb0 display should probably be attached to the component view."

     

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