Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

Project Samples

Lower do-while loops into ifs and gotos Sum numbers from 1 to 10: after transformation Sum numbers from 1 to 10: before transformation

Project Activity

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Categories

Code Generators, Compilers, Electronic Design Automation (EDA)

License

BSD License

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Additional Project Details

Intended Audience

Information Technology, Science/Research, Developers

User Interface

Command-line

Programming Language

C++, VHDL/Verilog

Related Categories

C++ Code Generators, C++ Compilers, C++ Electronic Design Automation (EDA) Software, VHDL/Verilog Code Generators, VHDL/Verilog Compilers, VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2006-10-16
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