[Hackndev-commit] SF.net SVN: hackndev: [1250] linux4palm/linux/trunk

[<mar...@us...>]

Revision: 1250
          http://hackndev.svn.sourceforge.net/hackndev/?rev=1250&view=rev
Author:   marex_z71
Date:     2007-08-20 15:56:19 -0700 (Mon, 20 Aug 2007)

Log Message:
-----------
PalmTX: more realistic approach of NAND flash driver ... iolines mapped to CS1 and gpio driven control lines

Modified Paths:
--------------
    linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
    linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h

Modified: linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c
===================================================================
--- linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-20 17:05:21 UTC (rev 1249)
+++ linux4palm/linux/trunk/drivers/mtd/nand/palmtx.c	2007-08-20 22:56:19 UTC (rev 1250)
@@ -31,6 +31,19 @@
 #include <asm/memory.h>
 #include <asm/mach-types.h>
 
+/* Select the chip by setting nCE to low */
+#define NAND_CTL_SETNCE		1
+/* Deselect the chip by setting nCE to high */
+#define NAND_CTL_CLRNCE		2
+/* Select the command latch by setting CLE to high */
+#define NAND_CTL_SETCLE		3
+/* Deselect the command latch by setting CLE to low */
+#define NAND_CTL_CLRCLE		4
+/* Select the address latch by setting ALE to high */
+#define NAND_CTL_SETALE		5
+/* Deselect the address latch by setting ALE to low */
+#define NAND_CTL_CLRALE		6
+
 /*
  * MTD structure
  */
@@ -56,16 +69,34 @@
 
 /*
  *	hardware specific access to control-lines
- *
- *	NAND_NCE: bit 0 - don't care
- *	NAND_CLE: bit 1 - address bit 2
- *	NAND_ALE: bit 2 - address bit 3
  */
 static void palmtx_hwcontrol(struct mtd_info *mtd, int cmd,
 			    unsigned int ctrl)
 {
 	struct nand_chip *chip = mtd->priv;
 
+        if (ctrl & NAND_CTRL_CHANGE) {
+                switch (cmd) {
+                case NAND_CTL_SETCLE:
+                        SET_PALMTX_GPIO(NAND_CLE,1);
+                        break;
+                case NAND_CTL_CLRCLE:
+                        SET_PALMTX_GPIO(NAND_CLE,0);
+                        break;
+                case NAND_CTL_SETALE:
+                        SET_PALMTX_GPIO(NAND_ALE,1);
+                        break;
+                case NAND_CTL_CLRALE:
+                        SET_PALMTX_GPIO(NAND_ALE,0);
+                        break;
+                case NAND_CTL_SETNCE:
+                        SET_PALMTX_GPIO(NAND_NCE,1);
+                        break;
+                case NAND_CTL_CLRNCE:
+                        SET_PALMTX_GPIO(NAND_NCE,0);
+                        break;
+                }
+        }
 	if (cmd != NAND_CMD_NONE)
 		writeb(cmd, (void __iomem *)((unsigned long)chip->IO_ADDR_W));
 }

Modified: linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h
===================================================================
--- linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-20 17:05:21 UTC (rev 1249)
+++ linux4palm/linux/trunk/include/asm-arm/arch-pxa/palmtx-gpio.h	2007-08-20 22:56:19 UTC (rev 1250)
@@ -97,7 +97,10 @@
 
 /* NAND Flash ... these GPIOs are probably incorrect! */
 #define GPIO_NR_PALMTX_NAND_POWER		19
-#define GPIO_NR_PALMTX_NAND_READY		37
+#define GPIO_NR_PALMTX_NAND_READY		115
+#define GPIO_NR_PALMTX_NAND_CLE			79
+#define GPIO_NR_PALMTX_NAND_ALE			113
+#define GPIO_NR_PALMTX_NAND_NCE			114
 
 
 /* INTERRUPTS */


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