Next gen hi speed RedPAC-PLL V6 [Vivado2019.2] FPGA and Gxsm support build

Update on the latest high speed PAC-PLL (Red Pitaya based) Gxsm / MK3-A810 add on with digital hi speed serial link.

After a long struggle redesigning and porting to the latest Vivado 2019.2 Xilinx FPGA development platform the feat it finally done and all seam working fine now.

Under the high speed FPGA hood:

• Reorganization, rebuild/design of almost every module under the hood. Better modularity and better timing pereformance.
• New input interpolation filter
• Redesigned DC-filter
• Better pipelined PAC/LMS
• Optimized controller structures
• Totally redesigend signal combine/selection and decimation module, more flexibility, more efficient
• Cleaned up BRAM interface
• McBSP serial link functionally unchanged and working great again after temporary design/timing hickups with new development tool
• Additional new delta-frequency controller for generic use, output via McBSP link to DSP -- good for NC-AFM dF control or SQDM, etc...
  ** NEW: optimized new version of the hi-speed serial (real time) RP-PAC-PLL to DSP data interface been build in a small series and can be made available at cost. Please contact the GXSM team.

Overhauled Zynq A9 support JSON interface with much more efficient real time / threaded tuning controller, new scope trigger schemes, etc.

Updated GXSM inet-json-control plugin to support all new features.

Stay safe everyone in those apocalyptic times
enjoy!

your GXSM admin
-Percy