From: Joshua F. <jm...@ka...> - 2004-04-23 00:51:02
|
Hi all, So looking at the USB design of the buddyboard (or daughterboard, which do you prefer?) a couple of us on the #gumstix list today (by the way if you're not on the list [and most of you aren't :0] you're missing out) noticed that the PXA255 design manual recommensds the following: The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This voltage divider can be implemented in a number of ways. The most robust and expensive solution is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and minimizes signal bounce. The more inexpensive solution is to use a 3.3V line buffer with 5 V tolerant inputs. This solution does not reduce signal bounce, so software must compensate by reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.[1] Looking at the skematic for the daughterboard it looks like the MAX823 chip is substituted in place of the MAX6348.[2] We concluded that there are some potential problems with that design (specifically, it looks like the PXA's input port is being driven above its own 3.3V Vcc). Any comments? [1]. Section 4.1, p. 55: ftp://download.intel.com/design/pca/applicationsprocessors/manuals/27869401.pdf [2]. http://www.gumstix.com/docs/schematic.jpg -- Joshua Ferraro http://kados.org |