From: Schlansker, K. <ksc...@fo...> - 2008-06-16 16:04:26
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I'm trying to implement section 8.4.11 of the processor developer's manual (32-bit i2s emulation using SSP) over the SSP2 port. I'm configuring the PXA to be in slave mode. Once I've configured the SSP registers and enabled the serial link by setting the SSE bit, I receive one transmit service request interrupt because the transmit fifo is empty. I service the interrupt by filling it (which is kind of pointless since I only care about receiving data, not sending it), and then I get no more interrupts. I've scoped out all of the signals and verified that my clocks are correct and data is being sent. The SSSR2 register says that the PXA is still "syncing slave signals" (the SSSR2[CSS] bit is set). I've tried the notes that suggest the master device should not send it's frame sync signal until the CSS bit is clear, but it does not seem to help. Could there be some conflict with another piece of code that is trying to use the 2nd serial port? My setup is a Verdex, netCF-vx, and a tweener. Here's how I'm configuring things: // configure GPIOs pxa_gpio_mode(GPIO19_SSPSCLK2_IN_MD); pxa_gpio_mode(GPIO14_SSPSFRM2_IN_MD); pxa_gpio_mode(GPIO11_SSPRXD2_MD); pxa_gpio_mode(GPIO13_SSPTXD2_MD); // disable serial port SSCR0_P(ssp_port) &= ~SSCR0_SSE; // configure serial registers //SSCR0: 0b0000_0000_0001_0000_0000_0000_0011_1111 //SSCR1: 0b0010_0011_1000_0000_0001_0011_0000_0011 //SSPSP: 0b0000_0010_0000_0000_0000_0000_0000_0000 SSCR0_P(ssp_port) = 0x0010003f; SSCR1_P(ssp_port) = 0x23801303; SSPSP_P(ssp_port) = 0x02000000; // enable serial port SSCR0_P(ssp_port) |= SSCR0_SSE; It looks like the GPIOs are set correctly: I'm using GPIO pins 11, 13, 14, & 19: root@gumstix-custom-verdex:~$ cat /proc/gpio/GPIO11 /proc/gpio/GPIO13 /proc/gpio/GPIO14 /proc/gpio/GPIO19 11 AF2 in clear 13 AF1 out clear 14 AF2 in set 19 AF1 in clear Thanks! -- kyle |