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From: <by...@nc...> - 2016-09-18 23:49:01
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I'll look at how hierarchy is handled with respect to escaped identifiers when I find a little bit more time. For now, try turning off View->Dynamic Resize. Grab the pane divider and drag it hard to the left. (You might have to attempt this a couple of times or do it before you add signals.) You should be able to make it any size you want. -Tony ---- "Walter F.J. Mueller" <w.f...@re...> wrote: > Hallo, > > I'm using > - Xilinx Vivado 2016.2 > - post-synthesis vhdl models generated by netlister > - ghdl 0.34dev with ghw output > - gtkwave V3.3.73 > > The generated models have sometimes signal names with '\', like > > top.tb_arty.uut.rlink.core.b2cd.\N_REGS[dataval]\ > > When I add them to the display the full hierarchy path is shown. > That happens for any 'hier max' setting larger than 1. An exception > is 'hier max' set to 1, in that case only the last name component > is shown. > > See attached screen shot for 'hier max' equal 3, the signal > names without '\' are shown with 3 name components, the ones > with '\' with all, starting from 'top.'. > > This is quite a nuisance because the 'Signals' pane is always as > wide as the longest name, and since full hierarchy path names tend > to be rather long in generated models, the 'Waves' pane gets > uncomfortably narrow. > > > With best regards, Walter > > > P.S.: Note that Vivado even generates signal names like > top.tb_arty.uut.\SMRB.I0\.\<const0>\ > top.tb_arty.uut.\SMRB.I0\.smrb.\RB_SRES[err]\ > > --> "SMRB.IO" apparently is one element of the hierarchy > --> gtkwave handles that correctly in the SST display > --> but again, always full path shown in 'Signals' pane |
