|
doc
|
2017-11-01
|
Vincent Bonnet
|
[ff534d]
Added WS, WC and WO1, corrected width assignati...
|
|
modules_common
|
2017-04-03
|
Vincent Bonnet
|
[13bfbf]
Added headers
|
|
modules_systemverilog
|
2017-11-01
|
Vincent Bonnet
|
[9dfae4]
Added registers number parameter
|
|
modules_verilog
|
2017-11-01
|
Vincent Bonnet
|
[9dfae4]
Added registers number parameter
|
|
modules_vhdl
|
2017-11-01
|
Vincent Bonnet
|
[9dfae4]
Added registers number parameter
|
|
.gitignore
|
2016-10-03
|
Vincent Bonnet
|
[54727f]
Added ignore files for GIT
|
|
class_register.rb
|
2017-11-01
|
Vincent Bonnet
|
[9dfae4]
Added registers number parameter
|
|
gen_regs.rb
|
2017-11-01
|
Vincent Bonnet
|
[9dfae4]
Added registers number parameter
|