Updated parameters into localparam (SV only)
Updated parameters into localparam (SV only)
Updated check mask computation
Added registers number parameter
Added WS, WC and WO1, corrected width assignation on RW clear/set fields, added automatically an register and an output when update is set
Updated write mask computation
Added the development folder
Added documentation clean executable
Updated documentation
Corrected read process and removed output creation for RC and RS
Corrected read process and removed output creation for RC and RS
Added byte signal use for set or clear operations option
Added missing file fordisplays generation (SV only)
Updated Verilog (and updated date in headers)
Added update signal priority option
Added RC (read clear) and RS (read set) field types
Added byte read enable option
Added byte read enable option
Added displays generation (SV only) when register value change
Added W1 field type support
Renamed RC field type in RCST (read constant)n and corrected byte write option
Updated generated code and added random values ...
Added SystemVerilog testbench (preliminary rele...
Corrected RC read
Corrected read behavior
Added headers
Added VHDL modules
Updated SystemVerilog modules according to new ...
Added SystemVerliog testbench package source
Added byte write
Updated VHDL modules
Added testbench package
Added release information in output header file
Updated parameters and signals naming, correcte...
Corrected clock enable signal generation
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Added RWU, RW0 and RW1 support in testbench
Added RWU, RW0 and RW1 field types and correcte...
Updated document
Added fields width definition
Added documentation
Removed spaces on printed code
Removed address and data width parameters
Corrected values width definition
Updated RW1 to ROW1 and RW0 to ROW0
Simplified the read process algo
Cosmectics
Added structure and changed wire and reg to logic
Corrected require into require_relative
Added SystemVerilog package generation
Added scripts in order to generate SystemVerilo...
Added SystemVerilog RTL include package and ent...
Added parameter size for field reset values
Added ignore files for GIT
Moved code into modules, and added Verilog modules
Separated class description and code configuration
Separated class description and code configuration
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Initial commit