Activity for gen_regs

  • gen_regs gen_regs released /gen-regs-code_r2.1.0.zip

  • Vincent Bonnet committed [d265ee]

    Updated parameters into localparam (SV only)

  • Vincent Bonnet committed [acb536]

    Updated parameters into localparam (SV only)

  • Vincent Bonnet committed [6306ff]

    Updated check mask computation

  • Vincent Bonnet committed [9dfae4]

    Added registers number parameter

  • Vincent Bonnet committed [ff534d]

    Added WS, WC and WO1, corrected width assignation on RW clear/set fields, added automatically an register and an output when update is set

  • Vincent Bonnet committed [e8c37a]

    Updated write mask computation

  • Vincent Bonnet committed [5bf8bc]

    Added the development folder

  • Vincent Bonnet committed [888488]

    Added documentation clean executable

  • Vincent Bonnet committed [ea6ff2]

    Updated documentation

  • gen_regs gen_regs released /gen-regs-code_r2.0.1.zip

  • Vincent Bonnet committed [62e03a]

    Corrected read process and removed output creation for RC and RS

  • Vincent Bonnet committed [e0d98d]

    Corrected read process and removed output creation for RC and RS

  • gen_regs gen_regs released /gen-regs-code_r2.0.0.zip

  • Vincent Bonnet committed [f0f5eb]

    Added byte signal use for set or clear operations option

  • Vincent Bonnet committed [f482d6]

    Added missing file fordisplays generation (SV only)

  • Vincent Bonnet committed [ca43e1]

    Updated Verilog (and updated date in headers)

  • Vincent Bonnet committed [6f254c]

    Added update signal priority option

  • Vincent Bonnet committed [b8c348]

    Added RC (read clear) and RS (read set) field types

  • Vincent Bonnet committed [0fa11d]

    Added byte read enable option

  • Vincent Bonnet committed [d514f5]

    Added byte read enable option

  • Vincent Bonnet committed [89ad17]

    Added displays generation (SV only) when register value change

  • Vincent Bonnet committed [254984]

    Added W1 field type support

  • Vincent Bonnet committed [cd0846]

    Renamed RC field type in RCST (read constant)n and corrected byte write option

  • Vincent Bonnet committed [bf70f1]

    Updated generated code and added random values ...

  • Vincent Bonnet committed [d6082c]

    Added SystemVerilog testbench (preliminary rele...

  • Vincent Bonnet committed [ec44a0]

    Corrected RC read

  • Vincent Bonnet committed [066050]

    Corrected read behavior

  • Vincent Bonnet committed [13bfbf]

    Added headers

  • Vincent Bonnet committed [e78d7a]

    Added VHDL modules

  • Vincent Bonnet committed [e0716d]

    Updated SystemVerilog modules according to new ...

  • Vincent Bonnet committed [def3e7]

    Added SystemVerliog testbench package source

  • Vincent Bonnet committed [04efef]

    Added byte write

  • Vincent Bonnet committed [832ec4]

    Updated VHDL modules

  • Vincent Bonnet committed [f7b3fe]

    Added testbench package

  • gen_regs gen_regs released /README.txt

  • gen_regs gen_regs released /gen_regs_r1.1.1.zip

  • Vincent Bonnet Vincent Bonnet committed [c18fd8]

    Added release information in output header file

  • Vincent Bonnet Vincent Bonnet committed [67f032]

    Updated parameters and signals naming, correcte...

  • gen_regs gen_regs released /gen_regs_r1.1.zip

  • Vincent Bonnet Vincent Bonnet committed [3489df]

    Corrected clock enable signal generation

  • Vincent Bonnet Vincent Bonnet modified a wiki page

    Home

  • gen_regs gen_regs released /gen_regs_r1.0.zip

  • Vincent Bonnet Vincent Bonnet committed [2efb17]

    Added RWU, RW0 and RW1 support in testbench

  • Vincent Bonnet Vincent Bonnet committed [724367]

    Added RWU, RW0 and RW1 field types and correcte...

  • Vincent Bonnet Vincent Bonnet committed [8cbd18]

    Updated document

  • Vincent Bonnet Vincent Bonnet committed [e47a6f]

    Added fields width definition

  • Vincent Bonnet Vincent Bonnet committed [7865f1]

    Added documentation

  • Vincent Bonnet Vincent Bonnet committed [8ef203]

    Removed spaces on printed code

  • Vincent Bonnet Vincent Bonnet committed [17c3ec]

    Removed address and data width parameters

  • Vincent Bonnet Vincent Bonnet committed [61537b]

    Corrected values width definition

  • Vincent Bonnet Vincent Bonnet committed [ec5d0e]

    Updated RW1 to ROW1 and RW0 to ROW0

  • Vincent Bonnet Vincent Bonnet committed [e06114]

    Simplified the read process algo

  • Vincent Bonnet Vincent Bonnet committed [399df6]

    Cosmectics

  • Vincent Bonnet Vincent Bonnet committed [f3f5d2]

    Added structure and changed wire and reg to logic

  • Vincent Bonnet Vincent Bonnet committed [b06a4e]

    Corrected require into require_relative

  • Vincent Bonnet Vincent Bonnet committed [965880]

    Added SystemVerilog package generation

  • Vincent Bonnet Vincent Bonnet committed [bb69b5]

    Added scripts in order to generate SystemVerilo...

  • Vincent Bonnet Vincent Bonnet committed [03d7d8]

    Added SystemVerilog RTL include package and ent...

  • Vincent Bonnet Vincent Bonnet committed [9e558f]

    Added parameter size for field reset values

  • Vincent Bonnet Vincent Bonnet committed [54727f]

    Added ignore files for GIT

  • Vincent Bonnet Vincent Bonnet committed [5b8349]

    Moved code into modules, and added Verilog modules

  • Vincent Bonnet Vincent Bonnet committed [57423e]

    Separated class description and code configuration

  • Vincent Bonnet Vincent Bonnet committed [7cc138]

    Separated class description and code configuration

  • Vincent Bonnet Vincent Bonnet modified a wiki page

    Home

  • Vincent Bonnet Vincent Bonnet modified a wiki page

    Home

  • Vincent Bonnet Vincent Bonnet committed [1dbcc3]

    Initial commit

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