ATMEGA4809 family chips

[cribcat]

Re: millis() indeed great news!

I think the TINY USART/TIMERs ...etc, are the same as the MEGA peripherals except for the number of USART/TIMERs. The Tinys have TCD and a DAC too. The setup and operation are nearly the same. Pretty much all of the code will be universal in AVR-0/1. Anyway... i hope that's the case.

I noticed AVRDUDE 8 has been released. It seems to communicate with my USB to Serial converter which will make life easier for those with raw chips and a serial device.
AVRDUDE 7 probably works fine as SerialUPDI, but more features have been added. Studying that to get up to speed.

[Anobium]

AVRDUDE is causing no end of issues. They are nor regression testing - they seem to forget to test.

We have had to backout the current AVRDUDE release and it cannot program LGTs and has acquired case sensitivity.

---

Great news on Timers and Millis.

Weekend off for me!

[cribcat]

Millis () seems to run fine on my hardware. Have a good weekend, I'd have to say you've earned it.

[Anobium]

Updated RAR ( I have moved from ZIP to RAR ).

https://1drv.ms/f/s!Ase-PX_n_4cvhP9oJsliPl4v9tm3Cg?e=dFDhsJ

The folders match you build, so, can drag and drop the contents now.

---

In the RAR is a set of demos for millis. I tested across a range of chips. All passed.

I have ported your ASM for:

100_MEGA4809_Set_Clock_Out.gcb
110_MEGA4809_Set_PWM.gcb

---

For the life of me... I cannot get PWM working at 38Hz using main clock as the primary clock source. So, this is not using the 32k as the main OSC but something between 2 to 20 mHz. Can you have a look? I tried MPLAB... failed to do anything!

---

So, I am now working on EEPROM operations.

[Anobium]

EEPROM read and write of AVRDX

The EEPROM operations of EPWRITE() and EPREAD() are now support. Same syntax as legacy AVR, PIC etc.

I have written a demo program to write and read the EEPROM. This program write 256 EEPROM bytes - select from Random number, a fixed number, or a range ( 255 to 0 )

The program will output the results on a serial terminal as follows - this is a range

EEPROM Test and Show Results 

      00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 
000:  FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
010:  EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
020:  DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
030:  CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0
040:  BF BE BD BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
050:  AF AE AD AC AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
060:  9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90
070:  8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80
080:  7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70
090:  6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60
0A0:  5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50
0B0:  4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40
0C0:  3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30
0D0:  2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20
0E0:  1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10
0F0:  0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

End of EEProm Program and Display

Updated EEPROM.H is in the latest RAR, along with the demo.

---

Enjoy

[cribcat]

The TCB can only do a main clock of div 2, It is not like TCA. If You divide the Main Clock(OSC20M) by 64 then You can get the TCB PWM down to about 612 Hz, but then it may affect Millis() on TCA . TCA is the champion in the 4809 as far as PWM. TCB is a good interval counter.

I'm having anomalous issues with MICROCHIP( AKA.ATMEL) STUDIO 7 simulator. I have no debugger so I have to debug with USART and LEDs to verify that hardware works. Rumor has it that Microchip is not doing any bug fixes on microchip/atmel studio 7 software any longer. The Simulator will get no attention. I guess MPLAB X is the future.

Congrats on the EE R/W!

I'm working on flash write. The BOOTEND/APPEND fuses play a role in this. Figuring out what works. Got USERROW EEwrite coded, was having issues with simulator anomalies ... going to MPLAB X to see if it will work better.

Thanks for the update.

[Anobium]

EE R/W is totally based on your work.

The methods EPWRITE ( EEAddress , EEDataValue) and EEPREAD ( EEAddress ) { a function}. Are relatively simple.

Write the data to correct address, handled the interrupt ( in this case there is no interrupt defined so the compiler optimises that code .. by removing it ), then set the protect and execute the write. I even left your comments in!

;Source: eeprom.h (89)
EPWRITE:
;Poke ( 0x1400 + [word]EEAddress , EEDataValue )
    lds SysTemp1,EEADDRESS
    ldi SysTemp2,0
    add SysTemp1,SysTemp2
    mov MEMADR,SysTemp1
    ldi SysTemp2,0
    ldi SysTemp3,20
    adc SysTemp2,SysTemp3
    mov MEMADR_H,SysTemp2
    lds MEMDATA,EEDATAVALUE
    rcall   POKE
;INTOFF
;CPU_CCP = CPU_CCP_SPM_gc           ; unlock CCP change protection for NVM command register
    ldi SysValueCopy,157
    out CPU_CCP,SysValueCopy
;NVMCTRL_CTRLA = NVMCTRL_CMD_PAGEERASEWRITE_gc  ; execute NVM erase/write
    ldi SysValueCopy,3
    sts NVMCTRL_CTRLA,SysValueCopy
;Wait While NVMCTRL_STATUS.NVMCTRL_EEBUSY_bm
SysWaitLoop1:
    clr SysTemp1
    lds SysBitTest,NVMCTRL_STATUS
    sbrc    SysBitTest,2
    inc SysTemp1
    tst SysTemp1
    brne    SysWaitLoop1
;INTON
    ret

I do need you full name to attribute this work to you. :-)

[cribcat]

Still have to figure out an erase routine for USERROW ... probably just writing 0xFF.

The Flash Write needs the BOOTEND/ APPEND fuses specifically set. A default BOOTEND 0 : APPEND 0, turns the entire Flash into the BOOT section and no section can write to itself.

[Anobium]

This is the config of a CNANO board. Just so you know.

PERIOD = OFF
WINDOW = OFF
SLEEP = DIS
ACTIVE = DIS
SAMPFREQ = 1KHZ
LVL = BODLEVEL0
FREQSEL = 20MHZ
OSCLOCK = [ ]
EESAVE = [X]
RSTPINCFG = GPIO
CRCSRC = NOCRC
SUT = 64MS

WDTCFG = 0x00 (valid)
BODCFG = 0x00 (valid)
OSCCFG = 0x02 (valid)
SYSCFG0 = 0xC1 (valid)
SYSCFG1 = 0x07 (valid)
APPEND = 0x00 (valid)
BOOTEND = 0x00 (valid)

[Anobium]

Let me know when you have user row operating.

But, a thought. Why wont EPWRITE just work with a different offset? EE offset is 0x1400. What is USERROW? Cannot we just change the offset?

[cribcat]

The code controlling the main prescaler/OSC select was changing the division values intermittently. it may or may not have caused you some problems. Here's a new Routine.

[cribcat]

I think the EPWRITE will work fine with the 0x1300 offset in USERROW... That's essentially what the routine is, But it doesn't have an erase routine specific to it( Like EEER, EEPROM Erase) and it is persistent through Chip_Erase. Maybe I'll try the EEER EEPROM Erase on USERROW.

[cribcat]

You Have to write 0xFF to USERROW to erase it, you can erase the entire page of 64 bytes, or a byte at a time... the code is attached above as MEGA4809_USER_ROW_EEP_RW.asm along with the flash page write code.

[cribcat]

Don't think you need this demo code, but here it is just in case.

[Anobium]

See https://sourceforge.net/p/gcbasic/discussion/579125/thread/7fb3c8422f/?limit=250#1280

But, essentially Hugh never implemented any EEPROM operations and he never implemented creation of an EEP file from GCASM.

So, I have resolved. A lot of work but basically a case of changing the datamodel to support AVR EE data, and then using the data model throughout the compiler.

Along the way I hit lots of issues but all seems to be resolved.

The following with now correctly generate an EEP, there a lots of ways but these are the two typlical methods.

EEPROM myEEDataBlock // [ EE address ]
    1,2,3,4  // etc
END EEPROM

or

TABLE myTable STORE DATA
    1,2,3,4
End Table

// This TABLE needs a READTABLE command to store the data in the EE.  As no READTABLE means the table it not required. 

---

I also sorted a new programming interface using UPDI to program the PROGMEM and EEPROM. It is fast and easy to use.

---

Now I will sort the FLASH write etc. and, resolve the DATA blocks. Onwards and upwards.

[cribcat]

That's awesome, Keep up the good work!

[Anobium]

Progress is ok.

Working Read Progmem and Data Block(s). Write Progmem after I have resolved/implemented Read Progmem/Block.

Lots needed to be resolved. But, now able to compile in GCASM and using the ASM produced by GCBASIC get same results with AVRASM2. Issue remaining are counting progmem used and a proper implementation of PROGREAD() Currently, the ASM is in my program not a library.

I will post a video soon. Lots to do!

[Anobium]

Program Read and Data Blocks supported

You can now read Program Memory ( PROGMEM ) and create Data Block in PROGMEM. Very simple to read PROGMEM with ProgramRead ( ) - pass the address and you will get the word returned. In terms of DATA BLOCK define a block as WORD ( default ) or BYTE and the compiler will handle strings, numbers, constants etc.

DATA myLorem as Byte 
"Lorem ipsum dolor sit amet, consectetur adipiscing elit."
"\&013123"
0xFFFF
END DAT

The program below shows the fullprogram to read a DATA BLOCK that is treated as an ASCII string ( you can treat the data anyway you like ). Use ProgramRead() to get the data.

Build 1425 has this capability. Downlodad and apply https://1drv.ms/u/s!Ase-PX_n_4cvhYJj_acYp33tuKbuEQ?e=kzTUK4

Program to read DATA BLOCK using ProgramRead()

/*
    This program uses DATA blocks to create data sets in PROGMEM, then, use PROGREAD() to show a DATA block on a serial terminal.

    You may want to increase the Seral BPS.....

*/
#chip mega4809            //  Declare the Target Processor and Speed
#option explicit          //  Require Explicit declaration of Variables

#DEFINE USART3_BAUD_RATE 9600
#DEFINE USART3_TX_BLOCKING
#DEFINE USART3_DELAY OFF

'*****************************************************************************************************
'Main program commences here.. everything before this is setup for the board.
'Now assumes Serial Terminal is operational

HserPrintCRLF 2
wait 1 s
HSerPrintStringCRLF "Dump byte DATABLOCK to terminal - commencing"
Wait 1 s

Dim Value, DataOffset, Address as Word 

// Initial data offset value
DataOffset = 0

// Loop through until the data block ends
Do 
    // Addresses need to be twice reported values - that is the way AVRs work.
    Address = @MYLOREM * 2                  // Get base address
    Address = Address + DataOffset          // Calcualate next address

    ProgramRead ( Address, value )          // Get the word value of the next two bytes

    // Show bytes as ASCII, do not show 0x00, and exit on 0xFF

        //~ Do not show last char which is 0xFF,0xFF, so, exit
        If Value_H = 0xFF or [BYTE]Value = 0xFF Then 
            //~ Exit the loop and end
            Exit Do
        End if

        // The 0x00 could be a pad byte, so, do not print
        If [BYTE]Value <> 0x00 OR [BYTE]Value_H <> 0x00 Then 
            HSerPrint Chr([BYTE]Value)
        End If

        // Index to next word
        DataOffset = DataOffset + 2


Loop 

HserPrintCRLF 2
HSerPrintStringCRLF "Dump DATABLOCK to Terminal - ended"

End

---

Technical Review of changes

This change was specifially hard as compiler did not support AVR for DATABLOCKS or PROGREAD().

The first challenge was to get the GCBASIC compiler to produce ASM that that was 100% compatible with AVRASM2. Specifically, the correct format for Byte and Word data. AVR ASM is STRICT and there the GCBASIC has to be correct.

Assembly instructions also had to AVRASM2 strict. Z+ is not valid, when Z and z+ is. GCBASIC needs to be strict also.

To support Byte DATABLOCK where the WORD in program contains two bytes required many changes - padding when only one byte is used, counting Bytes rather than Words to provide the correct PROGMEM usage number, isolation of PIC operations and AVR operations ( they are very different in terms of ASM!) and other tweaks.

Greg had provided ASM example of the read operations so this part was easy! This meant the extending of the method PROGREAD() to support AVR using a mix of GCBASIC and ASM.

I am learning more and more about AVR ASM but I am learning how good Hugh was in creating the base compiler. For this change the architecture really helps.

• GCBASIC Language changes - none, As PROGREAD() and DATA BLOCK is already there.
• Preprocessor - no changes as the context of handling DATA BLOCKs has not changed.
• DATA BLOCK handling - isolation of PIC and AVR operations adding the strict AVR ASM controls. I also added a check for duplicate naming of DATABLOCKs
• GCASM - add support for .DB - data bytes.

---

Next, ProgramWrite..

I have ASM, from Greg, I have methods to see the changes on terminal... What can go wrong?

Once ProgramWrite is done I will complete Write UserRow, PageWrite and then I2C and SPI.

What is missing then?

[Anobium]

@cribcat

I need some here completing the [interrupt] section of the DAT file.

What I need is rather simple .... I need for each interrupt the interrupt enable bit and the clear interrupt bit. As you can see below I have done this for a few - but they are all needed.

Looks at an example

RTCOverflow:RTC_CNT,6,RTC_INTCTRL.RTC_OVF_bp,RTC_INTFLAGS.RTC_OVF_bp

The enable bit is RTC_INTCTRL.RTC_OVF_bp and the clear bit is RTC_INTFLAGS.RTC_OVF_bp.

We need the rest that are shown as ,,

No rush but this is needed.

Thank you!

Evan

---

It would be best to edit an existing DAT and send it to me.

[Interrupts]
'For specific details of the interrupts see the microcontroller datasheet
'The first parameter is the GCBASIC identifier used in user code to expose the specific interrupt
; CRCSCAN interrupt vectors
    NMIfromCRC:CRCSCAN_NMI,2,,
; BOD interrupt vectors
    BOD_VLM:BOD_VLM,4,,
; RTC interrupt vectors
    RTCOverflow:RTC_CNT,6,RTC_INTCTRL.RTC_OVF_bp,RTC_INTFLAGS.RTC_OVF_bp
        RTC_PIT:RTC_PIT,8,,
; CCL interrupt vectors
        CCL_CCL:CCL_CCL,10,,
; PORTA interrupt vectors
        PORTA_PORT:PORTA_PORT,12,,
; TCA0 interrupt vectors
    Timer0Overflow:TCA0_LUNF,14,TCA0_SINGLE_INTCTRL.TCA_SINGLE_OVF_bp,!TCA0_SINGLE_INTFLAGS.TCA_SINGLE_OVF_bp
        TCA0_HUNF:TCA0_HUNF,16,,
    Timer0Match0:TCA0_CMP0,18,,
    Timer0Match1:TCA0_CMP1,20,,
    Timer0Match2:TCA0_CMP2,22,,
; TCB0 interrupt vectors
        TCB0_INT:TCB0_INT,24,,
; TCB1 interrupt vectors
        TCB1_INT:TCB1_INT,26,,
; TWI0 interrupt vectors
        TWI0_TWIS:TWI0_TWIS,28,,
        TWI0_TWIM:TWI0_TWIM,30,,
; SPI0 interrupt vectors
        SPI0_INT:SPI0_INT,32,,
; USART0 interrupt vectors
    Usart0RXReady:USART0_RXC,34, USART0_CTRLA.USART_RXCIE_bp, USART0_STATUS.USART_RXCIF_bp
        USART0_DRE:USART0_DRE,36,,
        USART0_TXC:USART0_TXC,38,,
; PORTD interrupt vectors
        PORTD_PORT:PORTD_PORT,40,,
; AC0 interrupt vectors
        AC0_AC:AC0_AC,42,,
; ADC0 interrupt vectors
        ADC0_RESRDY:ADC0_RESRDY,44,,
        ADC0_WCOMP:ADC0_WCOMP,46,,
; PORTC interrupt vectors
        PORTC_PORT:PORTC_PORT,48,,
; TCB2 interrupt vectors
        TCB2_INT:TCB2_INT,50,,
; USART1 interrupt vectors
    Usart1RXReady:USART1_RXC,52,USART1_CTRLA.USART_RXCIE_bp,USART1_STATUS.USART_RXCIF_bp
        USART1_DRE:USART1_DRE,54,,
        USART1_TXC:USART1_TXC,56,,
; PORTF interrupt vectors
        PORTF_PORT:PORTF_PORT,58,,
; NVMCTRL interrupt vectors
        NVMCTRL_EE:NVMCTRL_EE,60,,
; USART2 interrupt vectors
    Usart2RXReady:USART2_RXC,62,USART2_CTRLA.USART_RXCIE_bp,USART2_STATUS.USART_RXCIF_bp
        USART2_DRE:USART2_DRE,64,,
        USART2_TXC:USART2_TXC,66,,
; PORTB interrupt vectors
        PORTB_PORT:PORTB_PORT,68,,
; PORTE interrupt vectors
        PORTE_PORT:PORTE_PORT,70,,
; TCB3 interrupt vectors
        TCB3_INT:TCB3_INT,72,,
; USART3 interrupt vectors
    Usart3RXReady:USART3_RXC,74,USART3_CTRLA.USART_RXCIE_bp,USART3_STATUS.USART_RXCIF_bp
        USART3_DRE:USART3_DRE,76,,
        USART3_TXC:USART3_TXC,78,,

[cribcat]

Ok, I will switch gears and work on the [interrupt] section of the DAT file. Currently trying to figure out TWI / i2c protocol for the m4809.

I imagined that the compiler side would be difficult. I don't envy your job... it's a big one!
From what I understand the AVR-0/1 processors have similar syntax as the X-mega chips so that may help us in the future.

As far as what's missing?... These new processors are feature rich. Now that some of the big chunks are out of the way, we will have to re-assess our progress to determine what's left and how in-depth we want to get.

Some of this is new to me and I'm having to research it, but I am learning .

G

[Anobium]

Thanks re Interrupts.

TWI will be need. I have written a state engine for the newer PICs. Is that what is needed? Meanwhile folks can use software I2C/TWI.

You are correct. Assess where are next week as a number of features we may decide to leave as ASM demos.

And, we are learning!!

[cribcat]

Not sure in what context I'm dealing with in the .DAT files. There are interrupts with Multiple sources using a single vector as well as configuration group bits... not sure what to do there. Anyway, pls check this and see if any of it is useable.

[Anobium]

I am stumped. I need some input to crack this issue.

The PROGRAMWrite is just not working. Tried for a few days but no joy yet.

Here is the state of play. The write operation returns NVMCTRL_STATUS.2 = 1. This bit will read '1' when a write error has happened. A write error could be writing to different sections before doing a page write or writing to a protected area. This bit is valid for the last operation.

To call the test sub the following is used:

    Address = FnLSL(@WORDNUMBERS, 1)                 // Get base address

    // This is tad complex but this, for this test, returns the base address for a page of PROGMEM.
    // CHIPMAPPED_PROGMEM_START = 0x4000
    // address = the address of the stuff we want to overwrite
    // CHIPPROGMEM_PAGE_SIZE = 128
    // So, for any address this will set the address to the page address 0 byte.
    Address = (CHIPMAPPED_PROGMEM_START + Address ) AND NOT (CHIPPROGMEM_PAGE_SIZE - 1)

    PROGRAMWRITE ( Address, 0x1234 )

The SUB code is relatively simple.

Sub PROGRAMWRITE (In SYSSTRINGA as Word , In xMemData as Word)

    // SYSSTRINGA is a word aliased to R26 & R27 therefore the X register.

    Dim xMemData As Word

    INTOFF

    dim ccount
    for ccount = 0 to 63
      // just write 128 words for this test
      // SYSTEMP1 is .R1 
      SYSTEMP1 = xMemData_H   // write Hi Byte
      st X+, SYSTEMP1

      SYSTEMP1 = xMemData     // Write Lo Byte
      st X+, SYSTEMP1
    next

    wait while NVMCTRL_STATUS.1 = 1 or NVMCTRL_STATUS.0 = 1

CPU_CCP = CPU_CCP_SPM_gc            ; unlock CCP change protection for NVM command register
    NVMCTRL_CTRLA = NVMCTRL_CMD_PAGEERASEWRITE_gc   ; execute NVM erase/write 

End Sub

I have tried settings fuse BOOT=0xC0 and APPEND=0xC0. And, many other numbers... No joy.

---

Any thoughts?

[Geoffrey Younger]

Hello Anobium,
Do these new chip still require the $55 - $AA sequence for EE memory ?
Geoffrey Younger

[Anobium]

These chips are very different. The PICs need the 55-AA sequence.

The issue was ... incorrect Constant usage by me.

All resolved now.