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[Gc-linux-cvs] htdocs/xml/en news.xml,1.11,1.12 yagcd.xml,1.6,1.7
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From: <mi...@us...> - 2004-02-06 13:42:32
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Update of /cvsroot/gc-linux/htdocs/xml/en In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv942/xml/en Modified Files: news.xml yagcd.xml Log Message: ... Index: news.xml =================================================================== RCS file: /cvsroot/gc-linux/htdocs/xml/en/news.xml,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- news.xml 3 Feb 2004 02:53:33 -0000 1.11 +++ news.xml 6 Feb 2004 13:39:48 -0000 1.12 @@ -2,6 +2,21 @@ <?xml-stylesheet href="news.xsl" type="text/xsl"?> <news> <item> + <date>5 February 2004</date> + <title>Even more driver work</title> + <text>The keyboard driver works reliably now, and groepaz has contributed improved framebuffer code as well as a fricker-free framebuffer font.</text> + </item> + <item> + <date>4 February 2004</date> + <title>More driver work</title> + <text>kirin's audio driver (mknod /dev/dsp c 14 3) and Steve_-'s keyboard driver are in the CVS now. You can use your keyboard now, and you can output random noise...</text> + </item> + <item> + <date>3 February 2004</date> + <title>More drivers</title> + <text>kirin and Steve_- have contributed preliminary audio and keyboard drivers resp., and Costis and groepaz have increased the sharpness of the framebuffer. Expect fully integrated code in the CVS tomorrow.</text> + </item> + <item> <date>2 February 2004</date> <title><font color="red">GameCube Linux Alpha</font></title> <text>We have released a 1 MB busybox-based Linux system that contains screen output, network code, a telnet server and a webserver. We also provide a kernel patch. (<a href="docs/screenshots.html">Screenshots</a>/<a href="docs/download.html">Download</a>)</text> Index: yagcd.xml =================================================================== RCS file: /cvsroot/gc-linux/htdocs/xml/en/yagcd.xml,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- yagcd.xml 3 Feb 2004 01:23:37 -0000 1.6 +++ yagcd.xml 6 Feb 2004 13:39:48 -0000 1.7 @@ -9,7 +9,7 @@ <a href="../../down/yet_another_gamecube_doc.pdf.tar.gz">pdf</a> (primary document, recommended for printing)<br /> <hr /> -<small><b>last modified: Sat, 31 Jan 2004 22:46:41 </b></small><br /> +<small><b>last modified: Thu, 05 Feb 2004 09:04:41 </b></small><br /> <h1 align="center">Yet Another Gamecube Documentation<br /> <font size="-1">(but one that's worth printing)</font> </h1> @@ -475,7 +475,7 @@ <tr><td align="center">4</td><td>CLK</td></tr> -<tr><td align="center">5</td><td>1.25V</td></tr> +<tr><td align="center">5</td><td>12V</td></tr> <tr><td align="center">6</td><td>DO</td></tr> @@ -2180,7 +2180,7 @@ </table> </td></tr> -<tr><td align="center"><tt>0x800000d0</tt></td><td align="center"></td><td align="center"></td><td>?</td></tr> +<tr><td align="center"><tt>0x800000d0</tt></td><td align="center"></td><td align="center"></td><td>ARAM size (bytes or megabytes ?)</td></tr> <tr><td align="center"><tt>0x800000D4</tt></td><td align="center"></td><td align="center"></td><td>current OS Context (logical address)</td></tr> @@ -3270,10 +3270,12 @@ <tr><td align="center">29-31</td><td align="center">y</td><td>always zero (maybe some write only control register stuff?, setting bit 31 clears bits 31-28 (?))</td></tr> +<tr><td align="center">28</td><td align="center"></td><td>page offset bit (*1)</td></tr> + <tr><td align="center">24-27</td><td align="center">z</td><td>XOF - Horizontal Offset of the left-most pixel within the first word of the fetched picture.</td></tr> -<tr><td align="center">9-23</td><td align="center">a</td><td>FBB - bit 23 - bit 9 of XFB Address (*)</td></tr> +<tr><td align="center">9-23</td><td align="center">a</td><td>FBB - bit 23 - bit 9 of XFB Address (*2)</td></tr> <tr><td align="center">0-8</td><td align="center">x</td><td>unused (?)</td></tr> </table> @@ -3285,23 +3287,15 @@ <tr><td></td></tr> -<tr><td>(*) lowest possible Address: 0x80000000 (set register to 0x00000000)</td></tr> - -<tr><td></td></tr> - <tr><td>This register specifies the display origin of the top field of a picture in 2D mode or for the left picture in 3D mode</td></tr> - -<tr><td></td></tr> - -<tr><td>highest possible Address: 0x80fffe00 (set register to 0x00fffe00)</td></tr> - -<tr><td>as you can see the address must be aligned to 9 bits.</td></tr> - -<tr><td></td></tr> </table> <br /> <br /> +(*1) when this bit is set, the framebuffer address is calculated as (address> >5)<br /> +(*2) if bit 28 is cleared, highest possible Address: 0x80fffe00 (set register +to 0x00fffe00) (aligned to 9bit)<br /> +<br /> <table> <tr><td> @@ -3369,6 +3363,8 @@ <tr><td align="center"></td><td align="center">y</td><td>always zero (maybe some write-only control register stuff?)</td></tr> +<tr><td align="center">28</td><td align="center"></td><td>page offset bit (*1)</td></tr> + <tr><td align="center"></td><td align="center">a</td><td>FBB - bit 23 - bit 9 of XFB Address</td></tr> <tr><td align="center"></td><td align="center">x</td><td>unused (?)</td></tr> @@ -3388,6 +3384,8 @@ </table> <br /> <br /> +(*1) when this bit is set, the framebuffer address is calculated as (address> >5)<br /> +<br /> <table> <tr><td> @@ -6177,17 +6175,53 @@ </table> </td></tr> -<tr><td align="center">25-26</td><td align="center">c</td><td>Channel Number</td></tr> +<tr><td align="center">29</td><td align="center"></td><td>COMERR - Communication Error</td></tr> -<tr><td align="center"></td><td align="center"></td><td></td></tr> +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">0</td><td>ok</td></tr> -<tr><td align="center"></td><td align="center">s</td><td>Channel Enable (?)</td></tr> +<tr><td align="center">1</td><td>error (see SiSr for the cause)</td></tr> +</table> +</td></tr> -<tr><td align="center">16-22</td><td align="center">m</td><td>number of bytes we want in return, AND 0x7f</td></tr> +<tr><td align="center">28</td><td align="center"></td><td>RDSTINT - Read Status Interrupt Status (*2)</td></tr> -<tr><td align="center">8-14</td><td align="center">n</td><td>number of bytes we want to send, AND 0x7f</td></tr> +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>Transfer Complete Interrupt not requested</td></tr> -<tr><td align="center"></td><td align="center">e</td><td>Command Enable (?)</td></tr> +<tr><td align="center"></td><td align="center">1</td><td>Transfer Complete Interrupt has been requested</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td></td></tr> + +<tr><td align="center"></td><td align="center">1</td><td></td></tr> +</table> +</td></tr> + +<tr><td align="center">27</td><td align="center"></td><td>RDSTINTMSK - Read Status interrupt Mask (*3)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">0</td><td>masked</td></tr> + +<tr><td align="center">1</td><td>enabled</td></tr> +</table> +</td></tr> + +<tr><td align="center">25-26</td><td align="center">c</td><td>Channel Number (?)</td></tr> + +<tr><td align="center">24</td><td align="center">s</td><td>Channel Enable (?)</td></tr> + +<tr><td align="center">23</td><td align="center"></td><td>unused/reserved</td></tr> + +<tr><td align="center">16-22</td><td align="center">m</td><td>OUTLNGTH - Communication Channel Output Length (*4)</td></tr> + +<tr><td align="center">15</td><td align="center"></td><td>unused/reserved</td></tr> + +<tr><td align="center">8-14</td><td align="center">n</td><td>INLNGTH - Communication Channel Input Length (*4)</td></tr> + +<tr><td align="center">7</td><td align="center">e</td><td>Command Enable (?)</td></tr> <tr><td align="center">6</td><td align="center">b</td><td>callback enable</td></tr> @@ -6200,6 +6234,34 @@ <tr><td align="center">1</td><td>callback enabled</td></tr> </table> </td></tr> + +<tr><td align="center">1-2</td><td align="center"></td><td>CHANNEL - (*5)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">00</td><td>Channel 1</td></tr> + +<tr><td align="center">01</td><td>Channel 2</td></tr> + +<tr><td align="center">10</td><td>Channel 3</td></tr> + +<tr><td align="center">11</td><td>Channel 4</td></tr> +</table> +</td></tr> + +<tr><td align="center">0</td><td align="center"></td><td>TSTART - Transfer Start (*6)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>Command Complete</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Command Pending</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td>Do not start command</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Start command</td></tr> +</table> +</td></tr> </table> </td></tr> @@ -6209,6 +6271,21 @@ <tt></tt> <br /> (*1) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of SICOMCSR[TCINT]<tt></tt> <br /> +(*2) On read this bit indicates the current status of the Read Status interrupt. +The interrupt is set whenever SISR[RDSTn] bits are set. The interrupt is cleared +when all of the RdSt bits in the SISR are cleared by reading from the Si Channel +Input Buffers. This interrupt can be used to indicate that a polling transfer has +completed and new data is captured in the input registers<br /> +(*3) Interrupt masking prevents the interrupt from being sent to the main processor, +but does not affect the assertion of SICOMCSR[RDSTINT]<br /> +(*4) Minimum transfer is 1 byte. A value of 0 will transfer 128 bytes. These bits +should not be modified while SICOM transfer is in progress.<br /> +(*5) These bits should not be modified while SICOM transfer is in progress.<br /> +(*6) When a `1` is written to this register, the current communication transfer +is executed. The transfer begins immediately after the current transaction on this +channel has completed. When read this bit represents the current transfer status. +Once a communication transfer has been executed, polling will resume at the next +vblank if the channel's SIPOLL[ENn] bit is set.<tt></tt> <br /> <tt></tt> <br /> When programming the SICOMCSR after a SICOM transfers has already started (e.g., SICOMCSR[TSTART] is set), the software should read the current value first, @@ -6223,7 +6300,7 @@ <table> <tr><td><tt></tt> <table border="1" cellspacing="0" cellpadding="3"> -<tr><td align="center"><tt>0xCC006438</tt></td><td align="center">4</td><td align="center">r/w</td><td align="center">SISI - SI Status Register (channel select & status2)</td></tr> +<tr><td align="center"><tt>0xCC006438</tt></td><td align="center">4</td><td align="center">r/w</td><td align="center">SISR - SI Status Register (channel select & status2)</td></tr> </table> </td></tr> @@ -6259,17 +6336,81 @@ <tr><td align="center">30</td><td align="center"></td><td>reserved/unused</td></tr> -<tr><td align="center">29</td><td align="center"></td><td></td></tr> +<tr><td align="center">29</td><td align="center"></td><td>RDST0 - Read Status SIC0OINBUF Register (*2)</td></tr> -<tr><td align="center">28</td><td align="center"></td><td></td></tr> +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">0</td><td>New data available, not read by main processor</td></tr> -<tr><td align="center">27</td><td align="center"></td><td></td></tr> +<tr><td align="center">1</td><td>No new data available, already read by main processor</td></tr> +</table> +</td></tr> -<tr><td align="center">26</td><td align="center"></td><td></td></tr> +<tr><td align="center">28</td><td align="center"></td><td>WRST0 - Write Status SIC0OUTBUF Register (*3)</td></tr> -<tr><td align="center">25</td><td align="center"></td><td></td></tr> +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">0</td><td>Buffer copied</td></tr> -<tr><td align="center">24</td><td align="center"></td><td></td></tr> +<tr><td align="center">1</td><td>Buffer not copied</td></tr> +</table> +</td></tr> + +<tr><td align="center">27</td><td align="center"></td><td>NOREP0 - No Response Error Channel 0 (*4)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>No Response Error not asserted</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>No Response Error asserted</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td>No effect</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Clear No Response Error</td></tr> +</table> +</td></tr> + +<tr><td align="center">26</td><td align="center"></td><td>COLL0 - Collision Error Channel 0 (*5)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>Collision Error not asserted</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Collision Error asserted</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td>No effect</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Clear Collision Error</td></tr> +</table> +</td></tr> + +<tr><td align="center">25</td><td align="center"></td><td>OVRUN0 - Over Run Error Channel 0 (*6)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>Over Run Error not asserted</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Over Run Error asserted</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td>No effect</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Clear Over Run Error</td></tr> +</table> +</td></tr> + +<tr><td align="center">24</td><td align="center"></td><td>UNRUN - Under Run Error Channel 0 (*7)</td></tr> + +<tr><td align="center"></td><td align="center"></td><td> +<table border="1" cellspacing="0" cellpadding="3"> +<tr><td align="center">read</td><td align="center">0</td><td>Under Run not asserted</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Under Run asserted</td></tr> + +<tr><td align="center">write</td><td align="center">0</td><td>No effect</td></tr> + +<tr><td align="center"></td><td align="center">1</td><td>Clear Under Run Error</td></tr> +</table> +</td></tr> <tr><td align="center">22-23</td><td align="center"></td><td>reserved/unused</td></tr> @@ -6291,7 +6432,25 @@ <tt></tt> <br /> (*1) Write SICnOUTBUF Register: This register controls and indicates whether the SICnOUTBUFs have been copied to the double buffered output buffers. This bit is -cleared after the buffers have been copied.<tt></tt> <br /> +cleared after the buffers have been copied.<br /> +(*2) This register indicates whether the SIC0INBUFs have been captured new data +and whether the data has already been read by the main processor (read indicated +by main processor read of SIC01NBUF[ERRSTAT, ERRLATCH, INPUT0, INPUT1)]<br /> +(*3) This register indicates whether the SIC0OUTBUFs have been copied to the double +buffered output buffers. This bit is cleared after the buffers have been copied.<br /> +(*4) This register indicates that a previous transfer resulted in no response +from the controller. This can also be used to detect whether a controller is connected. +If no controller is connected, this bit will be set. Once set this bit remains set +until it is cleared by the main processor. To clear this bit write `1` to this register.<br /> +(*5) This register indicates data collision between controller and main unit. +Once set this bit remains set until it is cleared by the main processor. To clear +this bit write `1` to this register.<br /> +(*6) This register indicates that the main unit has received more data than expected. +Once set this bit remains set until it is cleared by the main processor. To clear +this bit write `1' to this register.<br /> +(*7) This register indicates that the main unit has received less data than expected. +Once set this bit remain set until it is cleared by the main processor. To clear +this bit write `1` to this register.<br /> <tt></tt> <br /> <tt></tt> <table> @@ -7650,7 +7809,7 @@ <tr><td align="center"></td></tr></table> </center> <div class="p"><!----></div> - <br /> + <table> <tr><td> <table border="1" cellspacing="0" cellpadding="3"> @@ -9990,7 +10149,7 @@ <tr><td align="center"></td></tr></table> </center> <div class="p"><!----></div> -<br /> + <table> <tr><td> <table border="1" cellspacing="0" cellpadding="3"> @@ -11274,10 +11433,10 @@ </table> <tt></tt> <br /> <tt></tt> <br /> -<tt>(*1) n: use light #n for bump map direction source (10 to 17)</tt> <br /> -<tt>(*2) n: use regular transformed tex(n) for bump mapping source</tt> <br /> -<tt>(*3) Specifies location of incoming textures in vertex (row specific) -(i.e.: geometry is row0, normal is row1, etc . . . ) for regular transformations</tt> <br /> +(*1) n: use light #n for bump map direction source (10 to 17)<br /> +(*2) n: use regular transformed tex(n) for bump mapping source<br /> +(*3) Specifies location of incoming textures in vertex (row specific) (i.e.: geometry +is row0, normal is row1, etc . . . ) for regular transformations<tt></tt> <br /> <tt></tt> <br /> <table> @@ -11790,7 +11949,7 @@ <div class="p"><!----></div> <h4><a name="tth_sEc6.2.4"> -6.2.4</a>  Pixel Engine Finished</h4> +6.2.4</a>  PE - Pixel Engine Finished</h4> <div class="p"><!----></div> 1 Source (Frame finished) @@ -11822,7 +11981,7 @@ <div class="p"><!----></div> <h4><a name="tth_sEc6.2.5"> -6.2.5</a>  Pixel Engine Token</h4> +6.2.5</a>  PE - Pixel Engine Token</h4> <div class="p"><!----></div> 1 Source (Token in GP Command List) @@ -11911,6 +12070,9 @@  </b> <div class="p"><!----></div> +asserted when audio DMA transfer has been completed. + +<div class="p"><!----></div> <br />    <b><a name="tth_sEc6.2.8.1.1"> 6.2.8.1.1  Setup</a>  </b> @@ -11933,11 +12095,27 @@ </ul> <div class="p"><!----></div> + +<b>6.2.8.2<a name="tth_sEc6.2.8.2"> +   ARAM transfer complete</a> + </b> + +<div class="p"><!----></div> +asserted when a transfer from/to auxiliary ram has been completed. + +<div class="p"><!----></div> + +<b>6.2.8.3<a name="tth_sEc6.2.8.3"> +   DSP</a> + </b> + +<div class="p"><!----></div> <h4><a name="tth_sEc6.2.9"> 6.2.9</a>  Audio Streaming Interface</h4> <div class="p"><!----></div> -1 Source, check (<tt>0xcc006c00</tt>) for flag +1 Source, check (<tt>0xcc006c00</tt>) for flag. asserted based on the disk streaming +sample counter. <div class="p"><!----></div> <h4><a name="tth_sEc6.2.10"> @@ -12665,6 +12843,23 @@ </ul> <div class="p"><!----></div> + <h4><a name="tth_sEc9.5.3"> +9.5.3</a>  Checksums</h4> + +<div class="p"><!----></div> +<tt>void checksums (unsigned short *buf, unsigned short *c1, unsigned short +*c2)</tt> <br /> +<tt>{</tt> <br /> +<tt>int i;</tt> <br /> +<tt>    *c1 = 0; *c2 = 0;</tt> <br /> +<tt>    for (i = 0;i<4;++i)</tt> <br /> +<tt>    {</tt> <br /> +<tt>        *c1 += buf[12 + i * 2];</tt> <br /> +<tt>        *c2 += (buf[12 + i * 2] 0xFFFF);</tt> <br /> +<tt>    }</tt> <br /> +<tt>}</tt> <br /> + +<div class="p"><!----></div> <h3><a name="tth_sEc9.6"> 9.6</a>  AD16</h3> @@ -16633,7 +16828,7 @@ <li> U.S. Pat. 6,411,301; 6,452,600; 6,466,218 (Graphics system interface) - GX Info</li> <li> U.S. Pat. 6,421,058 (Graphics command stream for calling a display object in a graphics -system) - GX Info</li> +system) - a lot of GX Info</li> <li> U.S. Pat. 6,424,348; 6,456,290; 6,489,963 (Application program interface for a graphics system) - GX Info</li> @@ -16671,6 +16866,10 @@ <li> U.S. Pat. 6,664,958 (Z-Texturing) - GX Info</li> <li> U.S. Pat. 6,664,962 (Shadow mapping in a low cost graphics system) - GX Info</li> + +<li> mx98726 Datasheet</li> + +<li> mx98728 Datasheet</li> </ul> <div class="p"><!----></div> @@ -16719,6 +16918,8 @@ <tr><td align="center"></td><td align="right">gcspec.html</td></tr> +<tr><td align="center"></td><td align="right">additional info in sram checksum, video regs</td></tr> + <tr><td align="center"><b>org </b></td><td align="right"><tt>kvz...@ma...</tt></td></tr> <tr><td align="center"></td><td align="right">additional apploader info / apploader RE</td></tr> @@ -16770,12 +16971,12 @@ <tr><td align="center"></td></tr></table> </center> <div class="p"><!----></div> -<br /><br />moreover, many thanks must go to everyone who helped making this document more consistant +moreover, many thanks must go to everyone who helped making this document more consistant and error free by proofreading and pointing out mistakes, in particular tmbinc, org, hubb, Aaron Kaluszka, Skywalker, Jihad, xor37h, costis, CrowTrobo, mist, ionic ...<br /> <br /> <br /> -<tt><b>EOT</b></tt> +EOT <br /><br /><hr /></iparticle> |
