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[Gc-linux-cvs] linux/drivers/usb/host ehci-hcd.c, NONE, 1.1 ehci.h, NONE, 1.1 ohci-hcd.c, NONE, 1.1 ohci-q.c, NONE, 1.1 ohci.h, NONE, 1.1 Kconfig, 1.7, 1.8
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From: Albert H. <he...@us...> - 2009-10-25 18:45:47
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Update of /cvsroot/gc-linux/linux/drivers/usb/host In directory ddv4jf1.ch3.sourceforge.com:/tmp/cvs-serv29988/drivers/usb/host Modified Files: Kconfig Added Files: ehci-hcd.c ehci.h ohci-hcd.c ohci-q.c ohci.h Log Message: Forward to v.2.6.30. --- NEW FILE: ohci-q.c --- /* * OHCI HCD (Host Controller Driver) for USB. * * (C) Copyright 1999 Roman Weissgaerber <we...@vi...> * (C) Copyright 2000-2002 David Brownell <dbr...@us...> * * This file is licenced under the GPL. */ #include <linux/irq.h> static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv) { int last = urb_priv->length - 1; if (last >= 0) { int i; struct td *td; [...1090 lines suppressed...] /* * Process normal completions (error or success) and clean the schedules. * * This is the main path for handing urbs back to drivers. The only other * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list, * instead of scanning the (re-reversed) donelist as this does. There's * an abnormal path too, handling a quirk in some Compaq silicon: URBs * with TDs that appear to be orphaned are directly reclaimed. */ static void dl_done_list (struct ohci_hcd *ohci) { struct td *td = dl_reverse_done_list (ohci); while (td) { struct td *td_next = td->next_dl_td; takeback_td(ohci, td); td = td_next; } } --- NEW FILE: ehci.h --- /* * Copyright (c) 2001-2002 by David Brownell * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #ifndef __LINUX_EHCI_HCD_H #define __LINUX_EHCI_HCD_H /* definitions used for the EHCI driver */ /* * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on * the host controller implementation. * * To facilitate the strongest possible byte-order checking from "sparse" * and so on, we use __leXX unless that's not practical. */ #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC typedef __u32 __bitwise __hc32; typedef __u16 __bitwise __hc16; #else #define __hc32 __le32 #define __hc16 __le16 #endif /* statistics can be kept for for tuning/monitoring */ struct ehci_stats { /* irq usage */ unsigned long normal; unsigned long error; unsigned long reclaim; unsigned long lost_iaa; /* termination of urbs from core */ unsigned long complete; unsigned long unlink; }; /* ehci_hcd->lock guards shared data against other CPUs: * ehci_hcd: async, reclaim, periodic (and shadow), ... * usb_host_endpoint: hcpriv * ehci_qh: qh_next, qtd_list * ehci_qtd: qtd_list * * Also, hold this lock when talking to HC registers or * when updating hw_* fields in shared qh/qtd/... structures. */ #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ struct ehci_hcd { /* one per controller */ /* glue to PCI and HCD framework */ struct ehci_caps __iomem *caps; struct ehci_regs __iomem *regs; struct ehci_dbg_port __iomem *debug; __u32 hcs_params; /* cached register copy */ spinlock_t lock; /* async schedule support */ struct ehci_qh *async; struct ehci_qh *reclaim; unsigned scanning : 1; /* periodic schedule support */ #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ unsigned periodic_size; __hc32 *periodic; /* hw periodic table */ dma_addr_t periodic_dma; unsigned i_thresh; /* uframes HC might cache */ union ehci_shadow *pshadow; /* mirror hw periodic table */ int next_uframe; /* scan periodic, start here */ unsigned periodic_sched; /* periodic activity count */ /* list of itds completed while clock_frame was still active */ struct list_head cached_itd_list; unsigned clock_frame; /* per root hub port */ unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; /* bit vectors (one bit per port) */ unsigned long bus_suspended; /* which ports were already suspended at the start of a bus suspend */ unsigned long companion_ports; /* which ports are dedicated to the companion controller */ unsigned long owned_ports; /* which ports are owned by the companion during a bus suspend */ unsigned long port_c_suspend; /* which ports have the change-suspend feature turned on */ unsigned long suspended_ports; /* which ports are suspended */ /* per-HC memory pools (could be per-bus, but ...) */ struct dma_pool *qh_pool; /* qh per active urb */ struct dma_pool *qtd_pool; /* one or more per qh */ struct dma_pool *itd_pool; /* itd per iso urb */ struct dma_pool *sitd_pool; /* sitd per split iso urb */ struct timer_list iaa_watchdog; struct timer_list watchdog; unsigned long actions; unsigned stamp; unsigned long next_statechange; u32 command; /* SILICON QUIRKS */ unsigned no_selective_suspend:1; unsigned has_fsl_port_bug:1; /* FreeScale */ unsigned big_endian_mmio:1; unsigned big_endian_desc:1; unsigned has_amcc_usb23:1; /* required for usb32 quirk */ #define OHCI_CTRL_HCFS (3 << 6) #define OHCI_USB_OPER (2 << 6) #define OHCI_USB_SUSPEND (3 << 6) #define OHCI_HCCTRL_OFFSET 0x4 #define OHCI_HCCTRL_LEN 0x4 __hc32 *ohci_hcctrl_reg; u8 sbrn; /* packed release number */ /* irq statistics */ #ifdef EHCI_STATS struct ehci_stats stats; # define COUNT(x) do { (x)++; } while (0) #else # define COUNT(x) do {} while (0) #endif /* debug files */ #ifdef DEBUG struct dentry *debug_dir; struct dentry *debug_async; struct dentry *debug_periodic; struct dentry *debug_registers; #endif }; /* convert between an HCD pointer and the corresponding EHCI_HCD */ static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) { return (struct ehci_hcd *) (hcd->hcd_priv); } static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) { return container_of ((void *) ehci, struct usb_hcd, hcd_priv); } static inline void iaa_watchdog_start(struct ehci_hcd *ehci) { WARN_ON(timer_pending(&ehci->iaa_watchdog)); mod_timer(&ehci->iaa_watchdog, jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); } static inline void iaa_watchdog_done(struct ehci_hcd *ehci) { del_timer(&ehci->iaa_watchdog); } enum ehci_timer_action { TIMER_IO_WATCHDOG, TIMER_ASYNC_SHRINK, TIMER_ASYNC_OFF, }; static inline void timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) { clear_bit (action, &ehci->actions); } static void free_cached_itd_list(struct ehci_hcd *ehci); /*-------------------------------------------------------------------------*/ #include <linux/usb/ehci_def.h> /*-------------------------------------------------------------------------*/ #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) /* * EHCI Specification 0.95 Section 3.5 * QTD: describe data transfer components (buffer, direction, ...) * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". * * These are associated only with "QH" (Queue Head) structures, * used with control, bulk, and interrupt transfers. */ struct ehci_qtd { /* first part defined by EHCI spec */ __hc32 hw_next; /* see EHCI 3.5.1 */ __hc32 hw_alt_next; /* see EHCI 3.5.2 */ __hc32 hw_token; /* see EHCI 3.5.3 */ #define QTD_TOGGLE (1 << 31) /* data toggle */ #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) #define QTD_IOC (1 << 15) /* interrupt on complete */ #define QTD_CERR(tok) (((tok)>>10) & 0x3) #define QTD_PID(tok) (((tok)>>8) & 0x3) #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ #define QTD_STS_HALT (1 << 6) /* halted on error */ #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ #define QTD_STS_STS (1 << 1) /* split transaction state */ #define QTD_STS_PING (1 << 0) /* issue PING? */ #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ __hc32 hw_buf_hi [5]; /* Appendix B */ /* the rest is HCD-private */ dma_addr_t qtd_dma; /* qtd address */ struct list_head qtd_list; /* sw qtd list */ struct urb *urb; /* qtd's urb */ size_t length; /* length of buffer */ } __attribute__ ((aligned (32))); /* mask NakCnt+T in qh->hw_alt_next */ #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) /*-------------------------------------------------------------------------*/ /* type tag from {qh,itd,sitd,fstn}->hw_next */ #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) /* * Now the following defines are not converted using the * cpu_to_le32() macro anymore, since we have to support * "dynamic" switching between be and le support, so that the driver * can be used on one system with SoC EHCI controller using big-endian * descriptors as well as a normal little-endian PCI EHCI controller. */ /* values for that type tag */ #define Q_TYPE_ITD (0 << 1) #define Q_TYPE_QH (1 << 1) #define Q_TYPE_SITD (2 << 1) #define Q_TYPE_FSTN (3 << 1) /* next async queue entry, or pointer to interrupt/periodic QH */ #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) /* for periodic/async schedules and qtd lists, mark end of list */ #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ /* * Entries in periodic shadow table are pointers to one of four kinds * of data structure. That's dictated by the hardware; a type tag is * encoded in the low bits of the hardware's periodic schedule. Use * Q_NEXT_TYPE to get the tag. * * For entries in the async schedule, the type tag always says "qh". */ union ehci_shadow { struct ehci_qh *qh; /* Q_TYPE_QH */ struct ehci_itd *itd; /* Q_TYPE_ITD */ struct ehci_sitd *sitd; /* Q_TYPE_SITD */ struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ __hc32 *hw_next; /* (all types) */ void *ptr; }; /*-------------------------------------------------------------------------*/ /* * EHCI Specification 0.95 Section 3.6 * QH: describes control/bulk/interrupt endpoints * See Fig 3-7 "Queue Head Structure Layout". * * These appear in both the async and (for interrupt) periodic schedules. */ struct ehci_qh { /* first part defined by EHCI spec */ __hc32 hw_next; /* see EHCI 3.6.1 */ __hc32 hw_info1; /* see EHCI 3.6.2 */ #define QH_HEAD 0x00008000 __hc32 hw_info2; /* see EHCI 3.6.2 */ #define QH_SMASK 0x000000ff #define QH_CMASK 0x0000ff00 #define QH_HUBADDR 0x007f0000 #define QH_HUBPORT 0x3f800000 #define QH_MULT 0xc0000000 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ /* qtd overlay (hardware parts of a struct ehci_qtd) */ __hc32 hw_qtd_next; __hc32 hw_alt_next; __hc32 hw_token; __hc32 hw_buf [5]; __hc32 hw_buf_hi [5]; /* the rest is HCD-private */ dma_addr_t qh_dma; /* address of qh */ union ehci_shadow qh_next; /* ptr to qh; or periodic */ struct list_head qtd_list; /* sw qtd list */ struct ehci_qtd *dummy; struct ehci_qh *reclaim; /* next to reclaim */ struct ehci_hcd *ehci; /* * Do NOT use atomic operations for QH refcounting. On some CPUs * (PPC7448 for example), atomic operations cannot be performed on * memory that is cache-inhibited (i.e. being used for DMA). * Spinlocks are used to protect all QH fields. */ u32 refcount; unsigned stamp; u8 qh_state; #define QH_STATE_LINKED 1 /* HC sees this */ #define QH_STATE_UNLINK 2 /* HC may still see this */ #define QH_STATE_IDLE 3 /* HC doesn't see this */ #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ u8 xacterrs; /* XactErr retry counter */ #define QH_XACTERR_MAX 32 /* XactErr retry limit */ /* periodic schedule info */ u8 usecs; /* intr bandwidth */ u8 gap_uf; /* uframes split/csplit gap */ u8 c_usecs; /* ... split completion bw */ u16 tt_usecs; /* tt downstream bandwidth */ unsigned short period; /* polling interval */ unsigned short start; /* where polling starts */ #define NO_FRAME ((unsigned short)~0) /* pick new start */ struct usb_device *dev; /* access to TT */ } __attribute__ ((aligned (32))); /*-------------------------------------------------------------------------*/ /* description of one iso transaction (up to 3 KB data if highspeed) */ struct ehci_iso_packet { /* These will be copied to iTD when scheduling */ u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ __hc32 transaction; /* itd->hw_transaction[i] |= */ u8 cross; /* buf crosses pages */ /* for full speed OUT splits */ u32 buf1; }; /* temporary schedule data for packets from iso urbs (both speeds) * each packet is one logical usb transaction to the device (not TT), * beginning at stream->next_uframe */ struct ehci_iso_sched { struct list_head td_list; unsigned span; struct ehci_iso_packet packet [0]; }; /* * ehci_iso_stream - groups all (s)itds for this endpoint. * acts like a qh would, if EHCI had them for ISO. */ struct ehci_iso_stream { /* first two fields match QH, but info1 == 0 */ __hc32 hw_next; __hc32 hw_info1; u32 refcount; u8 bEndpointAddress; u8 highspeed; u16 depth; /* depth in uframes */ struct list_head td_list; /* queued itds/sitds */ struct list_head free_list; /* list of unused itds/sitds */ struct usb_device *udev; struct usb_host_endpoint *ep; /* output of (re)scheduling */ unsigned long start; /* jiffies */ unsigned long rescheduled; int next_uframe; __hc32 splits; /* the rest is derived from the endpoint descriptor, * trusting urb->interval == f(epdesc->bInterval) and * including the extra info for hw_bufp[0..2] */ u8 usecs, c_usecs; u16 interval; u16 tt_usecs; u16 maxp; u16 raw_mask; unsigned bandwidth; /* This is used to initialize iTD's hw_bufp fields */ __hc32 buf0; __hc32 buf1; __hc32 buf2; /* this is used to initialize sITD's tt info */ __hc32 address; }; /*-------------------------------------------------------------------------*/ /* * EHCI Specification 0.95 Section 3.3 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" * * Schedule records for high speed iso xfers */ struct ehci_itd { /* first part defined by EHCI spec */ __hc32 hw_next; /* see EHCI 3.3.1 */ __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ __hc32 hw_bufp_hi [7]; /* Appendix B */ /* the rest is HCD-private */ dma_addr_t itd_dma; /* for this itd */ union ehci_shadow itd_next; /* ptr to periodic q entry */ struct urb *urb; struct ehci_iso_stream *stream; /* endpoint's queue */ struct list_head itd_list; /* list of stream's itds */ /* any/all hw_transactions here may be used by that urb */ unsigned frame; /* where scheduled */ unsigned pg; unsigned index[8]; /* in urb->iso_frame_desc */ } __attribute__ ((aligned (32))); /*-------------------------------------------------------------------------*/ /* * EHCI Specification 0.95 Section 3.4 * siTD, aka split-transaction isochronous Transfer Descriptor * ... describe full speed iso xfers through TT in hubs * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) */ struct ehci_sitd { /* first part defined by EHCI spec */ __hc32 hw_next; /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ __hc32 hw_uframe; /* EHCI table 3-10 */ __hc32 hw_results; /* EHCI table 3-11 */ #define SITD_IOC (1 << 31) /* interrupt on completion */ #define SITD_PAGE (1 << 30) /* buffer 0/1 */ #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ #define SITD_STS_ERR (1 << 6) /* error from TT */ #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ #define SITD_STS_XACT (1 << 3) /* illegal IN response */ #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ #define SITD_STS_STS (1 << 1) /* split transaction state */ #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) __hc32 hw_buf [2]; /* EHCI table 3-12 */ __hc32 hw_backpointer; /* EHCI table 3-13 */ __hc32 hw_buf_hi [2]; /* Appendix B */ /* the rest is HCD-private */ dma_addr_t sitd_dma; union ehci_shadow sitd_next; /* ptr to periodic q entry */ struct urb *urb; struct ehci_iso_stream *stream; /* endpoint's queue */ struct list_head sitd_list; /* list of stream's sitds */ unsigned frame; unsigned index; } __attribute__ ((aligned (32))); /*-------------------------------------------------------------------------*/ /* * EHCI Specification 0.96 Section 3.7 * Periodic Frame Span Traversal Node (FSTN) * * Manages split interrupt transactions (using TT) that span frame boundaries * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN * makes the HC jump (back) to a QH to scan for fs/ls QH completions until * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. */ struct ehci_fstn { __hc32 hw_next; /* any periodic q entry */ __hc32 hw_prev; /* qh or EHCI_LIST_END */ /* the rest is HCD-private */ dma_addr_t fstn_dma; union ehci_shadow fstn_next; /* ptr to periodic q entry */ } __attribute__ ((aligned (32))); /*-------------------------------------------------------------------------*/ #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT /* * Some EHCI controllers have a Transaction Translator built into the * root hub. This is a non-standard feature. Each controller will need * to add code to the following inline functions, and call them as * needed (mostly in root hub code). */ #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) /* Returns the speed of a device attached to a port on the root hub. */ static inline unsigned int ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) { if (ehci_is_TDI(ehci)) { switch ((portsc>>26)&3) { case 0: return 0; case 1: return (1<<USB_PORT_FEAT_LOWSPEED); case 2: default: return (1<<USB_PORT_FEAT_HIGHSPEED); } } return (1<<USB_PORT_FEAT_HIGHSPEED); } #else #define ehci_is_TDI(e) (0) #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) #endif /*-------------------------------------------------------------------------*/ #ifdef CONFIG_PPC_83xx /* Some Freescale processors have an erratum in which the TT * port number in the queue head was 0..N-1 instead of 1..N. */ #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) #else #define ehci_has_fsl_portno_bug(e) (0) #endif /* * While most USB host controllers implement their registers in * little-endian format, a minority (celleb companion chip) implement * them in big endian format. * * This attempts to support either format at compile time without a * runtime penalty, or both formats with the additional overhead * of checking a flag bit. */ #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) #else #define ehci_big_endian_mmio(e) 0 #endif /* * Big-endian read/write functions are arch-specific. * Other arches can be added if/when they're needed. */ #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) #define readl_be(addr) __raw_readl((__force unsigned *)addr) #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) #endif static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, __u32 __iomem * regs) { #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO return ehci_big_endian_mmio(ehci) ? readl_be(regs) : readl(regs); #else return readl(regs); #endif } static inline void ehci_writel(const struct ehci_hcd *ehci, const unsigned int val, __u32 __iomem *regs) { #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO ehci_big_endian_mmio(ehci) ? writel_be(val, regs) : writel(val, regs); #else writel(val, regs); #endif } /* * On certain ppc-44x SoC there is a HW issue, that could only worked around with * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. * Other common bits are dependant on has_amcc_usb23 quirk flag. */ #ifdef CONFIG_44x static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) { u32 hc_control; hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); if (operational) hc_control |= OHCI_USB_OPER; else hc_control |= OHCI_USB_SUSPEND; writel_be(hc_control, ehci->ohci_hcctrl_reg); (void) readl_be(ehci->ohci_hcctrl_reg); } #else static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) { } #endif /*-------------------------------------------------------------------------*/ /* * The AMCC 440EPx not only implements its EHCI registers in big-endian * format, but also its DMA data structures (descriptors). * * EHCI controllers accessed through PCI work normally (little-endian * everywhere), so we won't bother supporting a BE-only mode for now. */ #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC #define ehci_big_endian_desc(e) ((e)->big_endian_desc) /* cpu to ehci */ static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) { return ehci_big_endian_desc(ehci) ? (__force __hc32)cpu_to_be32(x) : (__force __hc32)cpu_to_le32(x); } /* ehci to cpu */ static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) { return ehci_big_endian_desc(ehci) ? be32_to_cpu((__force __be32)x) : le32_to_cpu((__force __le32)x); } static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) { return ehci_big_endian_desc(ehci) ? be32_to_cpup((__force __be32 *)x) : le32_to_cpup((__force __le32 *)x); } #else /* cpu to ehci */ static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) { return cpu_to_le32(x); } /* ehci to cpu */ static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) { return le32_to_cpu(x); } static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) { return le32_to_cpup(x); } #endif /*-------------------------------------------------------------------------*/ #ifndef DEBUG #define STUB_DEBUG_FILES #endif /* DEBUG */ /*-------------------------------------------------------------------------*/ #endif /* __LINUX_EHCI_HCD_H */ Index: Kconfig =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/Kconfig,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** Kconfig 25 Oct 2009 18:33:47 -0000 1.7 --- Kconfig 25 Oct 2009 18:45:36 -0000 1.8 *************** *** 25,32 **** "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. If your USB host controller supports USB 2.0, you will likely want to ! configure this Host Controller Driver. At the time of this writing, ! the primary implementation of EHCI is a chip from NEC, widely available ! in add-on PCI cards, but implementations are in the works from other ! vendors including Intel and Philips. Motherboard support is appearing. EHCI controllers are packaged with "companion" host controllers (OHCI --- 25,29 ---- "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. If your USB host controller supports USB 2.0, you will likely want to ! configure this Host Controller Driver. EHCI controllers are packaged with "companion" host controllers (OHCI *************** *** 124,128 **** config USB_ISP1760_HCD tristate "ISP 1760 HCD support" ! depends on USB && EXPERIMENTAL && (PCI || PPC_OF) ---help--- The ISP1760 chip is a USB 2.0 host controller. --- 121,125 ---- config USB_ISP1760_HCD tristate "ISP 1760 HCD support" ! depends on USB && EXPERIMENTAL ---help--- The ISP1760 chip is a USB 2.0 host controller. --- NEW FILE: ohci.h --- /* * OHCI HCD (Host Controller Driver) for USB. * * (C) Copyright 1999 Roman Weissgaerber <we...@vi...> * (C) Copyright 2000-2002 David Brownell <dbr...@us...> * * This file is licenced under the GPL. */ /* * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the * host controller implementation. */ typedef __u32 __bitwise __hc32; typedef __u16 __bitwise __hc16; /* * OHCI Endpoint Descriptor (ED) ... holds TD queue * See OHCI spec, section 4.2 * * This is a "Queue Head" for those transfers, which is why * both EHCI and UHCI call similar structures a "QH". */ struct ed { /* first fields are hardware-specified */ __hc32 hwINFO; /* endpoint config bitmap */ /* info bits defined by hcd */ #define ED_DEQUEUE (1 << 27) /* info bits defined by the hardware */ #define ED_ISO (1 << 15) #define ED_SKIP (1 << 14) #define ED_LOWSPEED (1 << 13) #define ED_OUT (0x01 << 11) #define ED_IN (0x02 << 11) __hc32 hwTailP; /* tail of TD list */ __hc32 hwHeadP; /* head of TD list (hc r/w) */ #define ED_C (0x02) /* toggle carry */ #define ED_H (0x01) /* halted */ __hc32 hwNextED; /* next ED in list */ /* rest are purely for the driver's use */ dma_addr_t dma; /* addr of ED */ struct td *dummy; /* next TD to activate */ /* host's view of schedule */ struct ed *ed_next; /* on schedule or rm_list */ struct ed *ed_prev; /* for non-interrupt EDs */ struct list_head td_list; /* "shadow list" of our TDs */ /* create --> IDLE --> OPER --> ... --> IDLE --> destroy * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... */ u8 state; /* ED_{IDLE,UNLINK,OPER} */ #define ED_IDLE 0x00 /* NOT linked to HC */ #define ED_UNLINK 0x01 /* being unlinked from hc */ #define ED_OPER 0x02 /* IS linked to hc */ u8 type; /* PIPE_{BULK,...} */ /* periodic scheduling params (for intr and iso) */ u8 branch; u16 interval; u16 load; u16 last_iso; /* iso only */ /* HC may see EDs on rm_list until next frame (frame_no == tick) */ u16 tick; } __attribute__ ((aligned(16))); #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */ /* * OHCI Transfer Descriptor (TD) ... one per transfer segment * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) * and 4.3.2 (iso) */ struct td { /* first fields are hardware-specified */ __hc32 hwINFO; /* transfer info bitmask */ /* hwINFO bits for both general and iso tds: */ #define TD_CC 0xf0000000 /* condition code */ #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) #define TD_DI 0x00E00000 /* frames before interrupt */ #define TD_DI_SET(X) (((X) & 0x07)<< 21) /* these two bits are available for definition/use by HCDs in both * general and iso tds ... others are available for only one type */ #define TD_DONE 0x00020000 /* retired to donelist */ #define TD_ISO 0x00010000 /* copy of ED_ISO */ /* hwINFO bits for general tds: */ #define TD_EC 0x0C000000 /* error count */ #define TD_T 0x03000000 /* data toggle state */ #define TD_T_DATA0 0x02000000 /* DATA0 */ #define TD_T_DATA1 0x03000000 /* DATA1 */ #define TD_T_TOGGLE 0x00000000 /* uses ED_C */ #define TD_DP 0x00180000 /* direction/pid */ #define TD_DP_SETUP 0x00000000 /* SETUP pid */ #define TD_DP_IN 0x00100000 /* IN pid */ #define TD_DP_OUT 0x00080000 /* OUT pid */ /* 0x00180000 rsvd */ #define TD_R 0x00040000 /* round: short packets OK? */ /* (no hwINFO #defines yet for iso tds) */ __hc32 hwCBP; /* Current Buffer Pointer (or 0) */ __hc32 hwNextTD; /* Next TD Pointer */ __hc32 hwBE; /* Memory Buffer End Pointer */ /* PSW is only for ISO. Only 1 PSW entry is used, but on * big-endian PPC hardware that's the second entry. */ #define MAXPSW 2 __hc16 hwPSW [MAXPSW]; /* rest are purely for the driver's use */ __u8 index; struct ed *ed; struct td *td_hash; /* dma-->td hashtable */ struct td *next_dl_td; struct urb *urb; dma_addr_t td_dma; /* addr of this TD */ dma_addr_t data_dma; /* addr of data it points to */ struct list_head td_list; /* "shadow list", TDs on same ED */ } __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */ #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */ /* * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW */ #define TD_CC_NOERROR 0x00 #define TD_CC_CRC 0x01 #define TD_CC_BITSTUFFING 0x02 #define TD_CC_DATATOGGLEM 0x03 #define TD_CC_STALL 0x04 #define TD_DEVNOTRESP 0x05 #define TD_PIDCHECKFAIL 0x06 #define TD_UNEXPECTEDPID 0x07 #define TD_DATAOVERRUN 0x08 #define TD_DATAUNDERRUN 0x09 /* 0x0A, 0x0B reserved for hardware */ #define TD_BUFFEROVERRUN 0x0C #define TD_BUFFERUNDERRUN 0x0D /* 0x0E, 0x0F reserved for HCD */ #define TD_NOTACCESSED 0x0F /* map OHCI TD status codes (CC) to errno values */ static const int cc_to_error [16] = { /* No Error */ 0, /* CRC Error */ -EILSEQ, /* Bit Stuff */ -EPROTO, /* Data Togg */ -EILSEQ, /* Stall */ -EPIPE, /* DevNotResp */ -ETIME, /* PIDCheck */ -EPROTO, /* UnExpPID */ -EPROTO, /* DataOver */ -EOVERFLOW, /* DataUnder */ -EREMOTEIO, /* (for hw) */ -EIO, /* (for hw) */ -EIO, /* BufferOver */ -ECOMM, /* BuffUnder */ -ENOSR, /* (for HCD) */ -EALREADY, /* (for HCD) */ -EALREADY }; /* * The HCCA (Host Controller Communications Area) is a 256 byte * structure defined section 4.4.1 of the OHCI spec. The HC is * told the base address of it. It must be 256-byte aligned. */ struct ohci_hcca { #define NUM_INTS 32 __hc32 int_table [NUM_INTS]; /* periodic schedule */ /* * OHCI defines u16 frame_no, followed by u16 zero pad. * Since some processors can't do 16 bit bus accesses, * portable access must be a 32 bits wide. */ __hc32 frame_no; /* current frame number */ __hc32 done_head; /* info returned for an interrupt */ u8 reserved_for_hc [116]; u8 what [4]; /* spec only identifies 252 bytes :) */ } __attribute__ ((aligned(256))); /* * This is the structure of the OHCI controller's memory mapped I/O region. * You must use readl() and writel() (in <asm/io.h>) to access these fields!! * Layout is in section 7 (and appendix B) of the spec. */ struct ohci_regs { /* control and status registers (section 7.1) */ __hc32 revision; __hc32 control; __hc32 cmdstatus; __hc32 intrstatus; __hc32 intrenable; __hc32 intrdisable; /* memory pointers (section 7.2) */ __hc32 hcca; __hc32 ed_periodcurrent; __hc32 ed_controlhead; __hc32 ed_controlcurrent; __hc32 ed_bulkhead; __hc32 ed_bulkcurrent; __hc32 donehead; /* frame counters (section 7.3) */ __hc32 fminterval; __hc32 fmremaining; __hc32 fmnumber; __hc32 periodicstart; __hc32 lsthresh; /* Root hub ports (section 7.4) */ struct ohci_roothub_regs { __hc32 a; __hc32 b; __hc32 status; #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */ __hc32 portstatus [MAX_ROOT_PORTS]; } roothub; /* and optional "legacy support" registers (appendix B) at 0x0100 */ } __attribute__ ((aligned(32))); /* OHCI CONTROL AND STATUS REGISTER MASKS */ /* * HcControl (control) register masks */ #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ /* pre-shifted values for HCFS */ # define OHCI_USB_RESET (0 << 6) # define OHCI_USB_RESUME (1 << 6) # define OHCI_USB_OPER (2 << 6) # define OHCI_USB_SUSPEND (3 << 6) /* * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR (1 << 0) /* host controller reset */ #define OHCI_CLF (1 << 1) /* control list filled */ #define OHCI_BLF (1 << 2) /* bulk list filled */ #define OHCI_OCR (1 << 3) /* ownership change request */ #define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* * masks used with interrupt registers: * HcInterruptStatus (intrstatus) * HcInterruptEnable (intrenable) * HcInterruptDisable (intrdisable) */ #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ #define OHCI_INTR_SF (1 << 2) /* start frame */ #define OHCI_INTR_RD (1 << 3) /* resume detect */ #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ #define OHCI_INTR_OC (1 << 30) /* ownership change */ #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ #define RH_PS_CCS 0x00000001 /* current connect status */ #define RH_PS_PES 0x00000002 /* port enable status*/ #define RH_PS_PSS 0x00000004 /* port suspend status */ #define RH_PS_POCI 0x00000008 /* port over current indicator */ #define RH_PS_PRS 0x00000010 /* port reset status */ #define RH_PS_PPS 0x00000100 /* port power status */ #define RH_PS_LSDA 0x00000200 /* low speed device attached */ #define RH_PS_CSC 0x00010000 /* connect status change */ #define RH_PS_PESC 0x00020000 /* port enable status change */ #define RH_PS_PSSC 0x00040000 /* port suspend status change */ #define RH_PS_OCIC 0x00080000 /* over current indicator change */ #define RH_PS_PRSC 0x00100000 /* port reset status change */ /* roothub.status bits */ #define RH_HS_LPS 0x00000001 /* local power status */ #define RH_HS_OCI 0x00000002 /* over current indicator */ #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ #define RH_HS_LPSC 0x00010000 /* local power status change */ #define RH_HS_OCIC 0x00020000 /* over current indicator change */ #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ /* roothub.b masks */ #define RH_B_DR 0x0000ffff /* device removable flags */ #define RH_B_PPCM 0xffff0000 /* port power control mask */ /* roothub.a masks */ #define RH_A_NDP (0xff << 0) /* number of downstream ports */ #define RH_A_PSM (1 << 8) /* power switching mode */ #define RH_A_NPS (1 << 9) /* no power switching */ #define RH_A_DT (1 << 10) /* device type (mbz) */ #define RH_A_OCPM (1 << 11) /* over current protection mode */ #define RH_A_NOCP (1 << 12) /* no over current protection */ #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* hcd-private per-urb state */ typedef struct urb_priv { struct ed *ed; u16 length; // # tds in this request u16 td_cnt; // tds already serviced struct list_head pending; struct td *td [0]; // all TDs in this request } urb_priv_t; #define TD_HASH_SIZE 64 /* power'o'two */ // sizeof (struct td) ~= 64 == 2^6 ... #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) /* * This is the full ohci controller description * * Note how the "proper" USB information is just * a subset of what the full implementation needs. (Linus) */ struct ohci_hcd { spinlock_t lock; /* * I/O memory used to communicate with the HC (dma-consistent) */ struct ohci_regs __iomem *regs; /* * main memory used to communicate with the HC (dma-consistent). * hcd adds to schedule for a live hc any time, but removals finish * only at the start of the next frame. */ struct ohci_hcca *hcca; dma_addr_t hcca_dma; struct ed *ed_rm_list; /* to be removed */ struct ed *ed_bulktail; /* last in bulk list */ struct ed *ed_controltail; /* last in ctrl list */ struct ed *periodic [NUM_INTS]; /* shadow int_table */ /* * OTG controllers and transceivers need software interaction; * other external transceivers should be software-transparent */ struct otg_transceiver *transceiver; void (*start_hnp)(struct ohci_hcd *ohci); /* * memory management for queue data structures */ struct dma_pool *td_cache; struct dma_pool *ed_cache; struct td *td_hash [TD_HASH_SIZE]; struct list_head pending; /* * driver state */ int num_ports; int load [NUM_INTS]; u32 hc_control; /* copy of hc control reg */ unsigned long next_statechange; /* suspend/resume */ u32 fminterval; /* saved register */ unsigned autostop:1; /* rh auto stopping/stopped */ unsigned long flags; /* for HC bugs */ #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ #define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */ #define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */ #define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */ #define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/ #define OHCI_QUIRK_NEC 0x40 /* lost interrupts */ #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */ #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ #define OHCI_QUIRK_AMD_ISO 0x200 /* ISO transfers*/ // there are also chip quirks/bugs in init logic struct work_struct nec_work; /* Worker for NEC quirk */ /* Needed for ZF Micro quirk */ struct timer_list unlink_watchdog; unsigned eds_scheduled; struct ed *ed_to_check; unsigned zf_delay; #ifdef DEBUG struct dentry *debug_dir; struct dentry *debug_async; struct dentry *debug_periodic; struct dentry *debug_registers; #endif }; #ifdef CONFIG_PCI static inline int quirk_nec(struct ohci_hcd *ohci) { return ohci->flags & OHCI_QUIRK_NEC; } static inline int quirk_zfmicro(struct ohci_hcd *ohci) { return ohci->flags & OHCI_QUIRK_ZFMICRO; } static inline int quirk_amdiso(struct ohci_hcd *ohci) { return ohci->flags & OHCI_QUIRK_AMD_ISO; } #else static inline int quirk_nec(struct ohci_hcd *ohci) { return 0; } static inline int quirk_zfmicro(struct ohci_hcd *ohci) { return 0; } static inline int quirk_amdiso(struct ohci_hcd *ohci) { return 0; } #endif /* convert between an hcd pointer and the corresponding ohci_hcd */ static inline struct ohci_hcd *hcd_to_ohci (struct usb_hcd *hcd) { return (struct ohci_hcd *) (hcd->hcd_priv); } static inline struct usb_hcd *ohci_to_hcd (const struct ohci_hcd *ohci) { return container_of ((void *) ohci, struct usb_hcd, hcd_priv); } /*-------------------------------------------------------------------------*/ #ifndef DEBUG #define STUB_DEBUG_FILES #endif /* DEBUG */ #define ohci_dbg(ohci, fmt, args...) \ dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) #define ohci_err(ohci, fmt, args...) \ dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) #define ohci_info(ohci, fmt, args...) \ dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) #define ohci_warn(ohci, fmt, args...) \ dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args ) #ifdef OHCI_VERBOSE_DEBUG # define ohci_vdbg ohci_dbg #else # define ohci_vdbg(ohci, fmt, args...) do { } while (0) #endif /*-------------------------------------------------------------------------*/ /* * While most USB host controllers implement their registers and * in-memory communication descriptors in little-endian format, * a minority (notably the IBM STB04XXX and the Motorola MPC5200 * processors) implement them in big endian format. * * In addition some more exotic implementations like the Toshiba * Spider (aka SCC) cell southbridge are "mixed" endian, that is, * they have a different endianness for registers vs. in-memory * descriptors. * * This attempts to support either format at compile time without a * runtime penalty, or both formats with the additional overhead * of checking a flag bit. * * That leads to some tricky Kconfig rules howevber. There are * different defaults based on some arch/ppc platforms, though * the basic rules are: * * Controller type Kconfig options needed * --------------- ---------------------- * little endian CONFIG_USB_OHCI_LITTLE_ENDIAN * * fully big endian CONFIG_USB_OHCI_BIG_ENDIAN_DESC _and_ * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO * * mixed endian CONFIG_USB_OHCI_LITTLE_ENDIAN _and_ * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC} * * (If you have a mixed endian controller, you -must- also define * CONFIG_USB_OHCI_LITTLE_ENDIAN or things will not work when building * both your mixed endian and a fully big endian controller support in * the same kernel image). */ #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN #define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC) #else #define big_endian_desc(ohci) 1 /* only big endian */ #endif #else #define big_endian_desc(ohci) 0 /* only little endian */ #endif #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO #ifdef CONFIG_USB_OHCI_LITTLE_ENDIAN #define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO) #else #define big_endian_mmio(ohci) 1 /* only big endian */ #endif #else #define big_endian_mmio(ohci) 0 /* only little endian */ #endif /* * Big-endian read/write functions are arch-specific. * Other arches can be added if/when they're needed. * */ static inline unsigned int _ohci_readl (const struct ohci_hcd *ohci, __hc32 __iomem * regs) { #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO return big_endian_mmio(ohci) ? readl_be (regs) : readl (regs); #else return readl (regs); #endif } static inline void _ohci_writel (const struct ohci_hcd *ohci, const unsigned int val, __hc32 __iomem *regs) { #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO big_endian_mmio(ohci) ? writel_be (val, regs) : writel (val, regs); #else writel (val, regs); #endif } #ifdef CONFIG_ARCH_LH7A404 /* Marc Singer: at the time this code was written, the LH7A404 * had a problem reading the USB host registers. This * implementation of the ohci_readl function performs the read * twice as a work-around. */ #define ohci_readl(o,r) (_ohci_readl(o,r),_ohci_readl(o,r)) #define ohci_writel(o,v,r) _ohci_writel(o,v,r) #else #define ohci_readl(o,r) _ohci_readl(o,r) #define ohci_writel(o,v,r) _ohci_writel(o,v,r) #endif /*-------------------------------------------------------------------------*/ /* cpu to ohci */ static inline __hc16 cpu_to_hc16 (const struct ohci_hcd *ohci, const u16 x) { return big_endian_desc(ohci) ? (__force __hc16)cpu_to_be16(x) : (__force __hc16)cpu_to_le16(x); } static inline __hc16 cpu_to_hc16p (const struct ohci_hcd *ohci, const u16 *x) { return big_endian_desc(ohci) ? cpu_to_be16p(x) : cpu_to_le16p(x); } static inline __hc32 cpu_to_hc32 (const struct ohci_hcd *ohci, const u32 x) { return big_endian_desc(ohci) ? (__force __hc32)cpu_to_be32(x) : (__force __hc32)cpu_to_le32(x); } static inline __hc32 cpu_to_hc32p (const struct ohci_hcd *ohci, const u32 *x) { return big_endian_desc(ohci) ? cpu_to_be32p(x) : cpu_to_le32p(x); } /* ohci to cpu */ static inline u16 hc16_to_cpu (const struct ohci_hcd *ohci, const __hc16 x) { return big_endian_desc(ohci) ? be16_to_cpu((__force __be16)x) : le16_to_cpu((__force __le16)x); } static inline u16 hc16_to_cpup (const struct ohci_hcd *ohci, const __hc16 *x) { return big_endian_desc(ohci) ? be16_to_cpup((__force __be16 *)x) : le16_to_cpup((__force __le16 *)x); } static inline u32 hc32_to_cpu (const struct ohci_hcd *ohci, const __hc32 x) { return big_endian_desc(ohci) ? be32_to_cpu((__force __be32)x) : le32_to_cpu((__force __le32)x); } static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x) { return big_endian_desc(ohci) ? be32_to_cpup((__force __be32 *)x) : le32_to_cpup((__force __le32 *)x); } /*-------------------------------------------------------------------------*/ /* HCCA frame number is 16 bits, but is accessed as 32 bits since not all * hardware handles 16 bit reads. That creates a different confusion on * some big-endian SOC implementations. Same thing happens with PSW access. */ #ifdef CONFIG_PPC_MPC52xx #define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO) #else #define big_endian_frame_no_quirk(ohci) 0 #endif static inline u16 ohci_frame_no(const struct ohci_hcd *ohci) { u32 tmp; if (big_endian_desc(ohci)) { tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no); if (!big_endian_frame_no_quirk(ohci)) tmp >>= 16; } else tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no); return (u16)tmp; } static inline __hc16 *ohci_hwPSWp(const struct ohci_hcd *ohci, const struct td *td, int index) { return (__hc16 *)(big_endian_desc(ohci) ? &td->hwPSW[index ^ 1] : &td->hwPSW[index]); } static inline u16 ohci_hwPSW(const struct ohci_hcd *ohci, const struct td *td, int index) { return hc16_to_cpup(ohci, ohci_hwPSWp(ohci, td, index)); } /*-------------------------------------------------------------------------*/ static inline void disable (struct ohci_hcd *ohci) { ohci_to_hcd(ohci)->state = HC_STATE_HALT; } #define FI 0x2edf /* 12000 bits per frame (-1) */ #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) #define FIT (1 << 31) #define LSTHRESH 0x628 /* lowspeed bit threshold */ static inline void periodic_reinit (struct ohci_hcd *ohci) { u32 fi = ohci->fminterval & 0x03fff; u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT; ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval, &ohci->regs->fminterval); ohci_writel (ohci, ((9 * fi) / 10) & 0x3fff, &ohci->regs->periodicstart); } /* AMD-756 (D2 rev) reports corrupt register contents in some cases. * The erratum (#4) description is incorrect. AMD's workaround waits * till some bits (mostly reserved) are clear; ok for all revs. */ #define read_roothub(hc, register, mask) ({ \ u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \ if (temp == -1) \ disable (hc); \ else if (hc->flags & OHCI_QUIRK_AMD756) \ while (temp & mask) \ temp = ohci_readl (hc, &hc->regs->roothub.register); \ temp; }) static inline u32 roothub_a (struct ohci_hcd *hc) { return read_roothub (hc, a, 0xfc0fe000); } static inline u32 roothub_b (struct ohci_hcd *hc) { return ohci_readl (hc, &hc->regs->roothub.b); } static inline u32 roothub_status (struct ohci_hcd *hc) { return ohci_readl (hc, &hc->regs->roothub.status); } static inline u32 roothub_portstatus (struct ohci_hcd *hc, int i) { return read_roothub (hc, portstatus [i], 0xffe0fce0); } --- NEW FILE: ohci-hcd.c --- /* * OHCI HCD (Host Controller Driver) for USB. * * (C) Copyright 1999 Roman Weissgaerber <we...@vi...> * (C) Copyright 2000-2004 David Brownell <dbr...@us...> * * [ Initialisation is based on Linus' ] * [ uhci code and gregs ohci fragments ] * [ (C) Copyright 1999 Linus Torvalds ] * [ (C) Copyright 1999 Gregory P. Smith] * * * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller * interfaces (though some non-x86 Intel chips use it). It supports * smarter hardware than UHCI. A download link for the spec available * through the http://www.usb.org website. * * This file is licenced under the GPL. */ [...1202 lines suppressed...] #endif #ifdef SA1111_DRIVER sa1111_driver_unregister(&SA1111_DRIVER); #endif #ifdef OF_PLATFORM_DRIVER of_unregister_platform_driver(&OF_PLATFORM_DRIVER); #endif #ifdef PLATFORM_DRIVER platform_driver_unregister(&PLATFORM_DRIVER); #endif #ifdef PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); #endif #ifdef DEBUG debugfs_remove(ohci_debug_root); #endif clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); } module_exit(ohci_hcd_mod_exit); --- NEW FILE: ehci-hcd.c --- /* * Copyright (c) 2000-2004 by David Brownell * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/module.h> [...1139 lines suppressed...] { #ifdef OF_PLATFORM_DRIVER of_unregister_platform_driver(&OF_PLATFORM_DRIVER); #endif #ifdef PLATFORM_DRIVER platform_driver_unregister(&PLATFORM_DRIVER); #endif #ifdef PCI_DRIVER pci_unregister_driver(&PCI_DRIVER); #endif #ifdef PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); #endif #ifdef DEBUG debugfs_remove(ehci_debug_root); #endif clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); } module_exit(ehci_hcd_cleanup); |
