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[Gc-linux-cvs] linux/drivers/usb/host Kconfig, 1.11, 1.12 Makefile, 1.8, 1.9 ehci-hcd.c, 1.4, 1.5 ehci.h, 1.4, 1.5 ohci-hcd.c, 1.4, 1.5 ohci-q.c, 1.3, 1.4 ohci.h, 1.3, 1.4
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From: Albert H. <he...@us...> - 2009-10-25 18:59:41
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Update of /cvsroot/gc-linux/linux/drivers/usb/host In directory ddv4jf1.ch3.sourceforge.com:/tmp/cvs-serv751/drivers/usb/host Modified Files: Kconfig Makefile ehci-hcd.c ehci.h ohci-hcd.c ohci-q.c ohci.h Log Message: Merge gc-linux-v2.6.31. Index: ohci-q.c =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/ohci-q.c,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** ohci-q.c 25 Oct 2009 18:53:45 -0000 1.3 --- ohci-q.c 25 Oct 2009 18:59:28 -0000 1.4 *************** *** 616,619 **** --- 616,622 ---- /* FALLTHROUGH */ case PIPE_BULK: + if (ohci->flags & OHCI_QUIRK_WII) + ohci_mipc_bulk_quirk(ohci); + info = is_out ? TD_T_TOGGLE | TD_CC | TD_DP_OUT *************** *** 647,650 **** --- 650,656 ---- */ case PIPE_CONTROL: + if (ohci->flags & OHCI_QUIRK_WII) + ohci_mipc_control_quirk(ohci); + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++); Index: ehci.h =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/ehci.h,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** ehci.h 25 Oct 2009 18:56:56 -0000 1.4 --- ehci.h 25 Oct 2009 18:59:28 -0000 1.5 *************** *** 38,41 **** --- 38,62 ---- #endif + /* + * Some platforms have weird constraints when accessing memory. + * + * For example, the Nintendo Wii video game console is unable to perform + * non-32 bit writes to non-cached memory for its second block of 64MB of RAM. + * As this platform also requires CONFIG_NOT_COHERENT, all memory allocated + * using the dma memory allocation functions can only be written using + * 32-bit accesses. + * + * Because of this constraint, as a workaround, we make sure that all + * fields in struct ehci_qh (which is allocated from a dma pool) are + * always 32 bit fields. + * Note that the remaining structs allocated from dma-able memory are already + * 32 bit fields. + */ + #ifdef CONFIG_USB_EHCI_HCD_MIPC + #define ehci_fld(type) u32 + #else + #define ehci_fld(type) type + #endif + /* statistics can be kept for for tuning/monitoring */ struct ehci_stats { *************** *** 337,341 **** unsigned stamp; ! u8 qh_state; #define QH_STATE_LINKED 1 /* HC sees this */ #define QH_STATE_UNLINK 2 /* HC may still see this */ --- 358,362 ---- unsigned stamp; ! ehci_fld(u8) qh_state; #define QH_STATE_LINKED 1 /* HC sees this */ #define QH_STATE_UNLINK 2 /* HC may still see this */ *************** *** 344,357 **** #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ ! u8 xacterrs; /* XactErr retry counter */ #define QH_XACTERR_MAX 32 /* XactErr retry limit */ /* periodic schedule info */ ! u8 usecs; /* intr bandwidth */ ! u8 gap_uf; /* uframes split/csplit gap */ ! u8 c_usecs; /* ... split completion bw */ ! u16 tt_usecs; /* tt downstream bandwidth */ ! unsigned short period; /* polling interval */ ! unsigned short start; /* where polling starts */ #define NO_FRAME ((unsigned short)~0) /* pick new start */ --- 365,378 ---- #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ ! ehci_fld(u8) xacterrs; /* XactErr retry counter */ #define QH_XACTERR_MAX 32 /* XactErr retry limit */ /* periodic schedule info */ ! ehci_fld(u8) usecs; /* intr bandwidth */ ! ehci_fld(u8) gap_uf; /* uframes split/csplit gap */ ! ehci_fld(u8) c_usecs; /* ... split completion bw */ ! ehci_fld(u16) tt_usecs; /* tt downstream bandwidth */ ! ehci_fld(unsigned short) period; /* polling interval */ ! ehci_fld(unsigned short) start; /* where polling starts */ #define NO_FRAME ((unsigned short)~0) /* pick new start */ *************** *** 592,595 **** --- 613,634 ---- #endif + #ifdef CONFIG_USB_EHCI_HCD_MIPC + + #include <asm/starlet-mini.h> + + static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, + __u32 __iomem *regs) + { + return mipc_in_be32(regs); + } + + static inline void ehci_writel(const struct ehci_hcd *ehci, + const unsigned int val, __u32 __iomem *regs) + { + mipc_out_be32(regs, val); + } + + #else + /* * Big-endian read/write functions are arch-specific. *************** *** 625,628 **** --- 664,669 ---- } + #endif /* CONFIG_USB_EHCI_HCD_MIPC */ + /* * On certain ppc-44x SoC there is a HW issue, that could only worked around with Index: Kconfig =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/Kconfig,v retrieving revision 1.11 retrieving revision 1.12 diff -C2 -d -r1.11 -r1.12 *** Kconfig 25 Oct 2009 18:56:56 -0000 1.11 --- Kconfig 25 Oct 2009 18:59:28 -0000 1.12 *************** *** 114,117 **** --- 114,125 ---- OpenFirmware platform bus. + config USB_EHCI_HCD_MIPC + bool "Nintendo Wii EHCI USB controller support via 'mini'" + depends on USB_EHCI_HCD && STARLET_MINI + default y + ---help--- + Say Y here to support the EHCI USB controller found in the + Nintendo Wii video game console. + config USB_OXU210HP_HCD tristate "OXU210HP HCD support" *************** *** 204,207 **** --- 212,224 ---- default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE + config USB_OHCI_HCD_MIPC + bool "Nintendo Wii OHCI USB controller support via 'mini'" + depends on USB_OHCI_HCD && STARLET_MINI + select USB_OHCI_LITTLE_ENDIAN + default y + ---help--- + Say Y here to support the OHCI USB controller found in the + Nintendo Wii video game console. + config USB_OHCI_HCD_PCI bool "OHCI support for PCI-bus USB controllers" *************** *** 344,347 **** --- 361,383 ---- SH7366, SH7723 and SH7724 processors. + config USB_WII_HCD + tristate "Nintendo Wii HCD support" + depends on USB && STARLET_IOS && !HIGHMEM && EXPERIMENTAL + help + The Nintendo Wii includes a USB 1.1 host controller that can be + accessed through the API provided by the starlet subsystem. + + Enable this option if you plan to use the internal Nintendo Wii + bluetooth dongle or any USB peripheral connected to the external + ports. + + USB devices using isochronous transfers are not supported. + Use of USB hubs is partially supported. + + Use completely at you own risk. If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called rvl-sthcd. + config USB_WHCI_HCD tristate "Wireless USB Host Controller Interface (WHCI) driver (EXPERIMENTAL)" Index: Makefile =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/Makefile,v retrieving revision 1.8 retrieving revision 1.9 diff -C2 -d -r1.8 -r1.9 *** Makefile 25 Oct 2009 18:56:56 -0000 1.8 --- Makefile 25 Oct 2009 18:59:28 -0000 1.9 *************** *** 31,33 **** --- 31,34 ---- obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o + obj-$(CONFIG_USB_WII_HCD) += rvl-sthcd.o obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o Index: ohci.h =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/ohci.h,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** ohci.h 25 Oct 2009 18:53:45 -0000 1.3 --- ohci.h 25 Oct 2009 18:59:28 -0000 1.4 *************** *** 17,20 **** --- 17,42 ---- /* + * Some platforms have weird constraints when accessing memory. + * + * For example, the Nintendo Wii video game console is unable to perform + * non-32 bit writes to non-cached memory for its second block of 64MB of RAM. + * As this platform also requires CONFIG_NOT_COHERENT_CACHE, all memory + * allocated using the dma memory allocation functions can only be written + * using 32-bit accesses. + * + * Because of this constraint, as a workaround, we make sure that all + * fields in struct ed and td (which are allocated from dma pools) are + * always 32 bit fields. + * Note that the remaining structs allocated from dma-able memory are already + * 32 bit fields. + */ + #ifdef CONFIG_USB_OHCI_HCD_MIPC + #define ohci_fld(type) u32 + #else + #define ohci_fld(type) type + #endif + + + /* * OHCI Endpoint Descriptor (ED) ... holds TD queue * See OHCI spec, section 4.2 *************** *** 52,70 **** * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... */ ! u8 state; /* ED_{IDLE,UNLINK,OPER} */ #define ED_IDLE 0x00 /* NOT linked to HC */ #define ED_UNLINK 0x01 /* being unlinked from hc */ #define ED_OPER 0x02 /* IS linked to hc */ ! u8 type; /* PIPE_{BULK,...} */ /* periodic scheduling params (for intr and iso) */ ! u8 branch; ! u16 interval; ! u16 load; ! u16 last_iso; /* iso only */ /* HC may see EDs on rm_list until next frame (frame_no == tick) */ ! u16 tick; } __attribute__ ((aligned(16))); --- 74,92 ---- * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... */ ! ohci_fld(u8) state; /* ED_{IDLE,UNLINK,OPER} */ #define ED_IDLE 0x00 /* NOT linked to HC */ #define ED_UNLINK 0x01 /* being unlinked from hc */ #define ED_OPER 0x02 /* IS linked to hc */ ! ohci_fld(u8) type; /* PIPE_{BULK,...} */ /* periodic scheduling params (for intr and iso) */ ! ohci_fld(u8) branch; ! ohci_fld(u16) interval; ! ohci_fld(u16) load; ! ohci_fld(u16) last_iso; /* iso only */ /* HC may see EDs on rm_list until next frame (frame_no == tick) */ ! ohci_fld(u16) tick; } __attribute__ ((aligned(16))); *************** *** 119,123 **** /* rest are purely for the driver's use */ ! __u8 index; struct ed *ed; struct td *td_hash; /* dma-->td hashtable */ --- 141,145 ---- /* rest are purely for the driver's use */ ! ohci_fld(__u8) index; struct ed *ed; struct td *td_hash; /* dma-->td hashtable */ *************** *** 403,406 **** --- 425,429 ---- #define OHCI_QUIRK_HUB_POWER 0x100 /* distrust firmware power/oc setup */ #define OHCI_QUIRK_AMD_ISO 0x200 /* ISO transfers*/ + #define OHCI_QUIRK_WII 0x400 /* Hollywood chipset */ // there are also chip quirks/bugs in init logic *************** *** 537,540 **** --- 560,594 ---- #endif + #ifdef CONFIG_USB_OHCI_HCD_MIPC + + #include <asm/starlet-mini.h> + + static inline unsigned int _ohci_readl(const struct ohci_hcd *ohci, + __hc32 __iomem *regs) + { + return mipc_in_be32(regs); + } + + static inline void _ohci_writel(const struct ohci_hcd *ohci, + const unsigned int val, __hc32 __iomem *regs) + { + mipc_out_be32(regs, val); + } + + extern void ohci_mipc_control_quirk(struct ohci_hcd *ohci); + extern void ohci_mipc_bulk_quirk(struct ohci_hcd *ohci); + + #else + + static inline void ohci_mipc_control_quirk(struct ohci_hcd *ohci) + { + return; + } + + static inline void ohci_mipc_bulk_quirk(struct ohci_hcd *ohci) + { + return; + } + /* * Big-endian read/write functions are arch-specific. *************** *** 566,569 **** --- 620,625 ---- } + #endif /* CONFIG_USB_OHCI_HCD_MIPC */ + #ifdef CONFIG_ARCH_LH7A404 /* Marc Singer: at the time this code was written, the LH7A404 Index: ohci-hcd.c =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/ohci-hcd.c,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** ohci-hcd.c 25 Oct 2009 18:56:56 -0000 1.4 --- ohci-hcd.c 25 Oct 2009 18:59:28 -0000 1.5 *************** *** 1062,1065 **** --- 1062,1070 ---- #endif + #ifdef CONFIG_USB_OHCI_HCD_MIPC + #include "ohci-mipc.c" + #define OF_PLATFORM_DRIVER ohci_hcd_mipc_driver + #endif + #ifdef CONFIG_PPC_PS3 #include "ohci-ps3.c" Index: ehci-hcd.c =================================================================== RCS file: /cvsroot/gc-linux/linux/drivers/usb/host/ehci-hcd.c,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** ehci-hcd.c 25 Oct 2009 18:56:56 -0000 1.4 --- ehci-hcd.c 25 Oct 2009 18:59:28 -0000 1.5 *************** *** 1108,1111 **** --- 1108,1116 ---- #endif + #ifdef CONFIG_USB_EHCI_HCD_MIPC + #include "ehci-mipc.c" + #define OF_PLATFORM_DRIVER ehci_hcd_mipc_driver + #endif + #ifdef CONFIG_PLAT_ORION #include "ehci-orion.c" |
