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[Gc-linux-devel] Gekko binutils patch
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From: Anders M M. <amm...@cc...> - 2004-05-02 16:11:09
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Hi, this is a in-progress patch for adding support for the Gekko
instructions to binutils (as and objdump). It's not well-tested at all,
and it's incomplete because the load and store instructions are still
missing because I don't really understand their encoding (eg. what do the
W and I fields represent?)
The patch is against current CVS, and any help testing/fixing/whatever is
appreciated.
To assemble Gekko instructions, pass "-mgekko" to as, and to disassemble
them pass "-Mgekko" to objdump.
-Anders
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.87
diff -u -r1.87 tc-ppc.c
--- gas/config/tc-ppc.c 7 Apr 2004 04:50:15 -0000 1.87
+++ gas/config/tc-ppc.c 2 May 2004 15:06:17 -0000
@@ -914,6 +914,9 @@
/* -many means to assemble for any architecture (PWR/PWRX/PPC). */
else if (strcmp (arg, "any") == 0)
ppc_cpu |= PPC_OPCODE_ANY;
+ else if (strcmp (arg, "gekko") == 0)
+ ppc_cpu = (PPC_OPCODE_CLASSIC | PPC_OPCODE_PPC
+ | PPC_OPCODE_32 | PPC_OPCODE_GEKKO);
else
return 0;
@@ -1106,6 +1109,7 @@
-maltivec generate code for AltiVec\n\
-me500, -me500x2 generate code for Motorola e500 core complex\n\
-mspe generate code for Motorola SPE instructions\n\
+-mgekko generate code for Gamecube Gekko\n\
-mregnames Allow symbolic names for registers\n\
-mno-regnames Do not allow symbolic names for registers\n"));
#ifdef OBJ_ELF
@@ -1150,6 +1154,9 @@
else
ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
}
+ else if (strcmp (default_cpu, "gekko") == 0)
+ ppc_cpu |= (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
+ | PPC_OPCODE_GEKKO);
else
as_fatal (_("Unknown default cpu = %s, os = %s"),
default_cpu, default_os);
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.17
diff -u -r1.17 ppc.h
--- include/opcode/ppc.h 16 Mar 2004 00:58:42 -0000 1.17
+++ include/opcode/ppc.h 25 Apr 2004 10:37:58 -0000
@@ -134,6 +134,9 @@
/* Opcode is supported by machine check APU. */
#define PPC_OPCODE_RFMCI 0x800000
+/* Opcode is only supported by PowerPC Gekko processor */
+#define PPC_OPCODE_GEKKO 0x1000000
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.16
diff -u -r1.16 ppc-dis.c
--- opcodes/ppc-dis.c 16 Mar 2004 00:58:41 -0000 1.16
+++ opcodes/ppc-dis.c 2 May 2004 10:59:25 -0000
@@ -91,6 +91,15 @@
dialect |= PPC_OPCODE_64;
}
+ if (info->disassembler_options)
+ {
+ if (strstr (info->disassembler_options, "gekko") != NULL)
+ {
+ dialect &= ~(PPC_OPCODE_ALTIVEC | PPC_OPCODE_403);
+ dialect |= PPC_OPCODE_GEKKO;
+ }
+ }
+
((struct dis_private *) &info->private_data)->dialect = dialect;
return dialect;
}
@@ -312,4 +321,5 @@
fprintf (stream, " power4 Disassemble the Power4 instructions\n");
fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
+ fprintf (stream, " gekko Disassemble the Gamecube Gekko instructions\n");
}
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.69
diff -u -r1.69 ppc-opc.c
--- opcodes/ppc-opc.c 30 Apr 2004 07:14:40 -0000 1.69
+++ opcodes/ppc-opc.c 1 May 2004 17:40:37 -0000
@@ -1786,6 +1786,7 @@
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI PPC_OPCODE_RFMCI
+#define PPCGEKKO PPC_OPCODE_GEKKO
/* The opcode table.
@@ -2343,6 +2344,61 @@
{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
+
+{ "ps_abs", XRC(4,264,0),XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_abs.", XRC(4,264,1),XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_add", A(4,21,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_add.", A(4,21,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_cmpo0", X(4,32),X_MASK|(3<<21), PPCGEKKO, { BF, FRA, FRB } },
+{ "ps_cmpo1", X(4,96),X_MASK|(3<<21), PPCGEKKO, { BF, FRA, FRB } },
+{ "ps_cmpu0", X(4,0), X_MASK|(3<<21), PPCGEKKO, { BF, FRA, FRB } },
+{ "ps_cmpu1", X(4,64),X_MASK|(3<<21), PPCGEKKO, { BF, FRA, FRB } },
+{ "ps_div", A(4,18,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_div.", A(4,18,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge00", A(4,528,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge00.",A(4,528,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge01", A(4,560,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge01.",A(4,560,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge10", A(4,597,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge10.",A(4,597,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge11", A(4,624,0), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_merge11.",A(4,624,1), AFRC_MASK, PPCGEKKO, { FRT, FRA, FRB } },
+{ "ps_mr", XRC(4,72,0), XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_mr.", XRC(4,72,1), XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_nabs", XRC(4,136,0),XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_nabs.", XRC(4,136,1),XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_neg", XRC(4,40,0), XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_neg.", XRC(4,40,1), XRA_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_res", A(4,24,0), AFRAFRC_MASK,PPCGEKKO, { FRT, FRB } },
+{ "ps_res.", A(4,24,1), AFRAFRC_MASK,PPCGEKKO, { FRT, FRB } },
+{ "ps_rsqrte", A(4,26,0), AFRAFRC_MASK,PPCGEKKO, { FRT, FRB } },
+{ "ps_rsqrte.", A(4,26,1), AFRAFRC_MASK,PPCGEKKO, { FRT, FRB } },
+{ "ps_sub", A(4,20,0), AFRC_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_sub.", A(4,20,1), AFRC_MASK, PPCGEKKO, { FRT, FRB } },
+{ "ps_madd", A(4,29,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_madd.", A(4,29,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_madds0", A(4,14,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_madds0.", A(4,14,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1", A(4,15,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_madds1.", A(4,15,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_msub", A(4,28,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_msub.", A(4,28,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_mul", A(4,25,0), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_mul.", A(4,25,1), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_muls0", A(4,12,0), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_muls0.", A(4,12,1), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_muls1", A(4,13,0), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_muls1.", A(4,13,1), AFRB_MASK, PPCGEKKO, { FRT, FRA, FRC } },
+{ "ps_nmadd", A(4,31,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_nmadd.", A(4,31,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub", A(4,30,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_nmsub.", A(4,30,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sel", A(4,23,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sel.", A(4,23,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sum0", A(4,10,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sum0.", A(4,10,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1", A(4,11,0), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
+{ "ps_sum1.", A(4,11,1), A_MASK, PPCGEKKO, { FRT,FRA,FRC,FRB } },
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
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