[CVS] drm-kernel radeon_cp.c,1.8,1.9 radeon_state.c,1.11,1.12

[<gat...@li...>]

Update of /cvsroot/gatos/drm-kernel
In directory sc8-pr-cvs1:/tmp/cvs-serv6611

Modified Files:
	radeon_cp.c radeon_state.c 
Log Message:
Reverse accidental removal of gatos-specific changes.


Index: radeon_cp.c
===================================================================
RCS file: /cvsroot/gatos/drm-kernel/radeon_cp.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** radeon_cp.c	26 Dec 2002 03:32:06 -0000	1.8
--- radeon_cp.c	26 Dec 2002 16:31:37 -0000	1.9
***************
*** 861,872 ****
  
  	/* Initialize the memory controller */
  	RADEON_WRITE( RADEON_MC_FB_LOCATION,
  		      (dev_priv->agp_vm_start - 1) & 0xffff0000 );
  
  	if ( !dev_priv->is_pci ) {
  		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
  			      (((dev_priv->agp_vm_start - 1 +
! 				 dev_priv->agp_size) & 0xffff0000) |
! 			       (dev_priv->agp_vm_start >> 16)) );
  	}
  
--- 861,883 ----
  
  	/* Initialize the memory controller */
+ 	#if 0
  	RADEON_WRITE( RADEON_MC_FB_LOCATION,
  		      (dev_priv->agp_vm_start - 1) & 0xffff0000 );
+ 	#endif
+ 	RADEON_WRITE( RADEON_MC_FB_LOCATION, 
+ 			((dev_priv->fb->offset>>16)&0xffff)|
+ 			((dev_priv->fb->offset+RADEON_READ(RADEON_CONFIG_APER_SIZE)-1)&0xffff0000));
+ 
+ 	RADEON_WRITE( RADEON_DISPLAY_BASE_ADDR, dev_priv->fb->offset);
+ 	RADEON_WRITE( RADEON_OVERLAY_BASE_ADDR, dev_priv->fb->offset);
+ 	RADEON_WRITE( RADEON_DEFAULT_OFFSET, 
+ 		(RADEON_READ(RADEON_DEFAULT_OFFSET) & (~0x3FFFFF)) |
+ 		((dev_priv->fb->offset>>10)& 0x3FFFFF));
  
  	if ( !dev_priv->is_pci ) {
  		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
  			      (((dev_priv->agp_vm_start - 1 +
! 				 dev_priv->agp_size+dev_priv->fb->offset) & 0xffff0000) |
! 			       ((dev_priv->agp_vm_start+dev_priv->fb->offset) >> 16)) );
  	}
  
***************
*** 882,886 ****
  			      + dev_priv->agp_vm_start);
  
! 	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
  
  	/* Set the write pointer delay */
--- 893,897 ----
  			      + dev_priv->agp_vm_start);
  
! 	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start+dev_priv->fb->offset);
  
  	/* Set the write pointer delay */
***************
*** 895,899 ****
  	if ( !dev_priv->is_pci ) {
  		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
! 			      dev_priv->ring_rptr->offset );
  	} else {
  		drm_sg_mem_t *entry = dev->sg;
--- 906,910 ----
  	if ( !dev_priv->is_pci ) {
  		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
! 			      dev_priv->ring_rptr->offset);
  	} else {
  		drm_sg_mem_t *entry = dev->sg;
***************
*** 1061,1069 ****
  
  	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
! 					(dev_priv->front_offset >> 10));
  	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
! 				       (dev_priv->back_offset >> 10));
  	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
! 					(dev_priv->depth_offset >> 10));
  
  	/* Hardware state for depth clears.  Remove this if/when we no
--- 1072,1080 ----
  
  	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
! 					(((dev_priv->front_offset) >> 10)&0x3FFFFF));
  	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
! 				       (((dev_priv->back_offset) >> 10)&0x3FFFFF));
  	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
! 					(((dev_priv->depth_offset) >> 10)&0x3FFFFF));
  
  	/* Hardware state for depth clears.  Remove this if/when we no

Index: radeon_state.c
===================================================================
RCS file: /cvsroot/gatos/drm-kernel/radeon_state.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** radeon_state.c	26 Dec 2002 03:32:06 -0000	1.11
--- radeon_state.c	26 Dec 2002 16:31:37 -0000	1.12
***************
*** 154,158 ****
  		OUT_RING( tex[0].pp_txfilter );
  		OUT_RING( tex[0].pp_txformat );
! 		OUT_RING( tex[0].pp_txoffset );
  		OUT_RING( tex[0].pp_txcblend );
  		OUT_RING( tex[0].pp_txablend );
--- 154,158 ----
  		OUT_RING( tex[0].pp_txfilter );
  		OUT_RING( tex[0].pp_txformat );
! 		OUT_RING( tex[0].pp_txoffset);
  		OUT_RING( tex[0].pp_txcblend );
  		OUT_RING( tex[0].pp_txablend );
***************
*** 168,172 ****
  		OUT_RING( tex[1].pp_txfilter );
  		OUT_RING( tex[1].pp_txformat );
! 		OUT_RING( tex[1].pp_txoffset );
  		OUT_RING( tex[1].pp_txcblend );
  		OUT_RING( tex[1].pp_txablend );
--- 168,172 ----
  		OUT_RING( tex[1].pp_txfilter );
  		OUT_RING( tex[1].pp_txformat );
! 		OUT_RING( tex[1].pp_txoffset);
  		OUT_RING( tex[1].pp_txcblend );
  		OUT_RING( tex[1].pp_txablend );
***************
*** 182,186 ****
  		OUT_RING( tex[2].pp_txfilter );
  		OUT_RING( tex[2].pp_txformat );
! 		OUT_RING( tex[2].pp_txoffset );
  		OUT_RING( tex[2].pp_txcblend );
  		OUT_RING( tex[2].pp_txablend );
--- 182,186 ----
  		OUT_RING( tex[2].pp_txfilter );
  		OUT_RING( tex[2].pp_txformat );
! 		OUT_RING( tex[2].pp_txoffset);
  		OUT_RING( tex[2].pp_txcblend );
  		OUT_RING( tex[2].pp_txablend );
***************
*** 893,897 ****
--- 893,901 ----
  	drm_radeon_private_t *dev_priv = dev->dev_private;
  	drm_clip_rect_t box;
+ #if 1
+ 	int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start + dev_priv->fb->offset;
+ #else	
  	int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
+ #endif
  	int numverts = (int)prim->numverts;
  	int i = 0;
***************
*** 968,972 ****
  	if ( start != end ) {
  		int offset = (dev_priv->agp_buffers_offset
! 			      + buf->offset + start);
  		int dwords = (end - start + 3) / sizeof(u32);
  
--- 972,976 ----
  	if ( start != end ) {
  		int offset = (dev_priv->agp_buffers_offset
! 			      + buf->offset + start+dev_priv->fb->offset);
  		int dwords = (end - start + 3) / sizeof(u32);
  
***************
*** 1002,1006 ****
  	drm_radeon_private_t *dev_priv = dev->dev_private;
  	drm_clip_rect_t box;
! 	int offset = dev_priv->agp_buffers_offset + prim->offset;
  	u32 *data;
  	int dwords;
--- 1006,1010 ----
  	drm_radeon_private_t *dev_priv = dev->dev_private;
  	drm_clip_rect_t box;
! 	int offset = dev_priv->agp_buffers_offset + prim->offset + dev_priv->fb->offset;
  	u32 *data;
  	int dwords;
***************
*** 1191,1195 ****
  		     RADEON_GMC_WR_MSK_DIS);
  
! 	buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
  	buffer[3] = 0xffffffff;
  	buffer[4] = 0xffffffff;
--- 1195,1199 ----
  		     RADEON_GMC_WR_MSK_DIS);
  
! 	buffer[2] = (tex->pitch << 22) | ((tex->offset) >> 10);
  	buffer[3] = 0xffffffff;
  	buffer[4] = 0xffffffff;
***************
*** 1199,1203 ****
  
  	buffer += 8;
- 
  	if ( tex_width >= 32 ) {
  		/* Texture image width is larger than the minimum, so we
--- 1203,1206 ----
***************
*** 1835,1839 ****
  	int sz = header.scalars.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = header.scalars.offset;
  	int stride = header.scalars.stride;
  	RING_LOCALS;
--- 1838,1842 ----
  	int sz = header.scalars.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = header.scalars.offset+dev_priv->fb->offset;
  	int stride = header.scalars.stride;
  	RING_LOCALS;
***************
*** 1859,1863 ****
  	int sz = header.scalars.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = ((unsigned int)header.scalars.offset) + 0x100;
  	int stride = header.scalars.stride;
  	RING_LOCALS;
--- 1862,1866 ----
  	int sz = header.scalars.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = ((unsigned int)header.scalars.offset+dev_priv->fb->offset) + 0x100;
  	int stride = header.scalars.stride;
  	RING_LOCALS;
***************
*** 1881,1885 ****
  	int sz = header.vectors.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = header.vectors.offset;
  	int stride = header.vectors.stride;
  	RING_LOCALS;
--- 1884,1888 ----
  	int sz = header.vectors.count;
  	int *data = (int *)cmdbuf->buf;
! 	int start = header.vectors.offset+dev_priv->fb->offset;
  	int stride = header.vectors.stride;
  	RING_LOCALS;
***************
*** 2176,2180 ****
  	switch( param.param ) {
  	case RADEON_PARAM_AGP_BUFFER_OFFSET:
! 		value = dev_priv->agp_buffers_offset;
  		break;
  	case RADEON_PARAM_LAST_FRAME:
--- 2179,2183 ----
  	switch( param.param ) {
  	case RADEON_PARAM_AGP_BUFFER_OFFSET:
! 		value = dev_priv->agp_buffers_offset + dev_priv->fb->offset;
  		break;
  	case RADEON_PARAM_LAST_FRAME:
***************
*** 2193,2197 ****
  		break;
  	case RADEON_PARAM_AGP_BASE:
! 		value = dev_priv->agp_vm_start;
  		break;
  	default:
--- 2196,2200 ----
  		break;
  	case RADEON_PARAM_AGP_BASE:
! 		value = dev_priv->agp_vm_start + dev_priv->fb->offset;
  		break;
  	default: