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Given a circuit described in terms of common CMOS logic gates, this is capable of minimizing logic area by repetitive examination of sets of three gates, utilizing a pre-computed lookup table of pre-optimized replacements. Reductions include XOR gates and can be extended to 3-input logic gates.
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Electronic Design Automation (EDA)License
GNU Library or Lesser General Public License version 3.0 (LGPLv3)Follow Fast Tabular Local Logic Minimizer
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