#111 dsPIC30F Silicon Erratum may cause crash with Address Trap

[Christenson]

See
https://sourceforge.net/p/freertos/discussion/382005/thread/8fdcda26/
for detailed description.

The silicon errata for dsPIC30F chips, including 30F4011/30F4013, 30F5011/30F5013 state that an address fault can be generated in the unlucky event that an interrupt is disabled in the same cycle it occurs. The errata gives workarounds, which simplify (non-recursive case) to disabling all interrupts on the cpu for the instructions that disable the interrupt or increase the privelege level, and continuing the disable for 4 additional cycles.

The portENTER_CRITICAL and portDISABLE_INTERRUPTS macros do not carry out this workaround.

for example.

__builtin_disi(0x3FF);

SRbits.IPL = configRTOS_PRIVELEGE_LEVEL;
// or
IEC0bits.T1IE = 0; // disable freeRTOS interrupt
// or 
IEC0bits.T1IF = 0; // skip an interrupt!

__builtin_disi(4);

[Christenson]

There are 24 Microchip dsPIC30F CPUs on Microchip's website.

The erratum affects:
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013

The erratum does not affect (at least per documentation):
dsPIC30F1010
dsPIC30F2020
dsPIC30F2023
dsPIC30F5015 (disi instruction still doesn't work if executed on the last cycle of a prior disi instruction)
dsPIC30F5016 (ditto)
dsPIC30F6010A (ditto)
dsPIC30F6015 (ditto)
dsPIC30F6011A (ditto, obsolete silicon revs only)
dsPIC30F6012A (ditto, obsolete silicon revs only)
dsPIC30F6013A (ditto, obsolete silicon revs only)
dsPIC30F6014A (ditto, obsolete silicon revs only)

I have not looked to see about other Microchip 16-bit CPU families.

[Richard Barry]

It looks like the SET_CPU_IPL macro is defined individually for each chip, so is there any reason why the code could not be changed as follows, to ensure the additional code for the errata work around is not included when chips that don't have the errata are used:

#define portDISABLE_INTERRUPTS()    SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY )
#define portENABLE_INTERRUPTS()     SET_CPU_IPL( 0 )

Also, is any errata workaround needed in the vPortYield function where interrupts are disabled?

Regards.