FPGA C Compiler / News: Recent posts

ReWrite getting started

After spending a few months looking at how to implement a complete ANSI-C compliance, a rewrite finally appears in order. This allows starting with an ANSI-C compliant grammar.

One goal is to split and restructure the current scope stack logic gating into a one hot for clock enables on local variables and state flow enables, plus a conditional stack for if-then-else, switch/case/default/break, and label/goto blocks.... read more

Posted by John Bass 2007-07-23

FpgaC.1.0.Beta-2 Released Today

FpgaC made a major milestone today releasing it's second Beta release with lots of new features.

Included are better Std C support, structures, small arrays, for-loops, and lots of cleanups.

Also included is preliminary support for various MS Windows compiler platforms in the projects mswin directory.

New examples of codeing Fpga's in C are provided, including a prototype for a PCI Target Mode interface.

Posted by John Bass 2006-03-03

FpgaC project is near to Beta-2 release

The FpgaC projects Beta-2F work-in-progress is now hosted on sf.net SVN subversion system. The current release canidate is in testing, and cleanup stages.

svn co https://svn.sourceforge.net/svnroot/fpgac/trunk/fpgac fpgac

We are looking for a Redhat/Fedora packager/maintainer to develop src/binary RPM's for the project. Also looking for a MS Windows developer to complete the initial MS Win port and package a MS Win binary release.

Posted by John Bass 2006-02-18

FpgaC team looking for a several more member

The FpgaC project is happy to announce that in the two weeks since created, we have a base release out, plus several developers have signed up to help. There are plenty of sub projects for several more developers at all skill levels. Additional sub project info in the forum discussions for FpgaC.

FpgaC compiles a subset of C to run on FPGAs instead of using a traditional CPU, a process called reconfigurable computing. FPGAs offer a high degree of parallelism for many algorithms by building a net list that executes statement blocks with gate level parallelism. In addition multiple threads may be concurrently active, with fast on chip communications, allow algorithm speed up of 1 to 3 orders of magnitude for computationally intensive applications.

Posted by John Bass 2005-11-17

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