Re: [Flashforth-devel] building FF5 for dsPIC33EP256GP502

[Peter J. <pe...@me...>]

Mike,
    Thanks for looking.  The flash write codes are different; I found a 
pair of tables in the migration guide.  The gains that I thought I would 
be receiving with the larger SRAM may be lost because I think that not 
all of that memory can be addressed with a 16-bit address (may have to 
set RAM_SIZE to 28k rather than the physically implemented 32k).  I 
expect that the buffers needed to deal with the larger erase blocks for 
the flash will be another loss (although I have not looked at how the 
flash self writing routines function).  On the aspects of the processor 
speed, the longer instruction execution pipeline on this MCU seems to 
suffer bigger penalties for branching than the dsPIC33FJ.  And without 
true EEPROM, it's looking not that much better a processor to spend much 
time on porting FF to it.
Regards,
Peter J.

On 11/07/14 19:39, Mikael Nordman wrote:
> Peter,
> I shortly looked at the datasheet.
>
> The  dsPIC33EP256GP502 does not have any alternate interrupt vector table.
>
> The change you have to do in FF is to revector the standard 
> /_default_/ interrupts to the interrupt table in ram which is managed 
> by FF, and there  handle the interrupt vectoring.
>
> Another difference is that the flash erase block is 1024 instructions 
> (3072  bytes). That should be reflected in  the configuration file.
> Also the flash write codes may be different. I have not checked.
>
> The eeprom emulation code for storing the dictionary pointers and the 
> turnkey may be affected. It is now written for a flash block erase 
> size of 1536 bytes.
>
> Good luck !
>
> BR Mike
>