Re: [Flashforth-devel] FF5.0 on PIC24FV32KA302 -- a couple of issues

[Peter J. <pe...@me...>]

Yes, the delay works nicely. Nothing missed in the following transcript, 
I believe.
Thank you.
Peter J


BPE FlashForth PIC24 5.0

2 3 * . 6  ok<#,ram>
   ok<#,ram>
   ok<#,ram>
words
true    false    Fcy    dump    allot    .s    words ms
ticks    r0    s0    latest    rhere    state    bl rdrop
endit    next    for    repeat    while    again until    begin
else    then    if    until,    again,    begin, else,    then,
if,    not,    nc,    z,    un,    in,    inline    [']
;i    ;    :noname    :    ]    [    does>    postpone
create    [char]    (    char    '    abort"    ?abort ?abort?
abort    prompt    quit    >dp    dp>    .st inlined    immediate
shb    interpret    in?    'source    >in    tiu tib    ti#
number?    >number    sign?    digit?    find immed?    (f)    c>n
n>c    @+    c@+    place    wmove    cmove    fill blanks
erase    word    parse    \    /string    source base    pad
hp    task    ssave    rsave    ulink    bin    hex decimal
hi    d.    ud.    .    u.r    u.    sign    #>
#s    #    >digit    <#    hold    up    min    max
?negate    tuck    nip    ud/mod    ud*    /    */ */mod
u*/mod    u/    *    u>    u<    d>    > d<
<    d=    =    <>    within    +!    ."    ,"
s"    (s")    type    >pr    .id    accept    1    0
umax    umin    spaces    space    cr    2dup    2drop 2!
2@    chars    char+    cells    cell+    aligned align    cell
c,    ,    here    dp    ram    eeprom    flash    xa>
 >xa    pfl    2constant    constant    co: 2variablevariable    >body
to    is    defer    value    user    mod    /mod u/mod
sm/rem    um/mod    m*    um*    s>d    p++    p2+ p+
pc!    p!    pc@    p@    @p    r>p    !p>r    !p
d0<    0<    d0=    0=    d2/    2/    d2*    2*
2-    1-    2+    1+    ?dnegate    dnegate    negate dinvert
invert    xor    or    and    d-    -    d+    m+
+    dabs    abs    r@    r>    >r    rot    over
swap    drop    rp0    rp@    sp@    sp!    (d)    (c)
exit    @ex    execute    dup    rx1?    rx1    tx1? tx1
u1rxq    u1txq    cq:    cq0    cq>?    cq> >cq?    >cq
'key?    'key    'emit    key?    key    emit    scan skip
n=    rshift    lshift    btst    bclr    bset    mtst mclr
mset    c@    @    c!    !    u1-    u1+    fl-
fl+    iflush    cf,    as,    cf@    cf!    btss, btsc,
btst,    bset,    bclr,    as0    bra,    retfie, return,    rcall,
operator    ei    di    i]    [i    aivt    ivt    int!
cwd    pause    turnkey    warm    empty    load busy    idle
a>    >a    literal
marker     ok<#,ram>



On 18/04/14 16:42, Mikael Nordman wrote:
> To verify that the UART errata is the problem
> insert a 1 or 2 millisecond delay in EMIT.
>
> EMIT:
>           mlit    2
>           rcall   MS
>           rcall   UEMIT
>           goto    FEXECUTE
>
> If it works, then it is clear that the UART TX interrupts cannot be
> trusted on  your chip.
>
> This can also be used as a simple workaround.
>
> I will also write polling TX routines that do not use interrupts.
> It only checks the TRMT flag. I think that should work with the UART bug.
>
> BR Mike
>
>
>
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