Re: [Flashforth-devel] FF 3.8 onto newer PIC18FxxK22 chips

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Thanks Attila,
I'll make that update.
Did you also change the clock source for the timers ?

Apparently the use if internal clock for TMR3 is not the default in 
18f2xK22.

BR Mike

On 09/16/2013 10:52 PM, Herman Attila wrote:
> Hi Craig and Mike
>
> The 18FxxK22 controllers are good choice, because they have several nice features. (2UARTS, 64MHz, lot of timers ...)
> If you want to use them, you have to modify the ff18_usb.asm file. The main problem with the using uart, the RX enable incompatibility. These controllers use ansela, anselb, anselc, anseld instead of ansel, anselh. The new RX enable routine:
> ; RX enable
> #ifdef ANSELH
> #ifdef ANS11
> 		bcf		ANSELH, ANS11, A ; Enable digital RB5 for RX
> #endif
> #endif
>
> #ifdef ANSELC
> #ifdef ANSC7
> 		BANKSEL		ANSELC
> 		bcf		ANSELC, ANSC7, BANKED   ; Enable digital RC7 for RX
> #endif
> #endif
>
>          movlw   b'10010000'
>          movwf   RCSTA, A
>          bsf     PIE1, RCIE, A
>
> You must use banked addressing, because anselc is out of range access bank!
>
> These controllers can run 64MHz with internal oscillator with PLL, but using this feature need a modification in FF. That's why the PLL enable in config bits is uneffective for the internal oscillator.
>
> #ifdef OSCCON
>          movlw   0x70            ; Use full internal OSC frequency
>          movwf   OSCCON, A
> #endif
> #ifdef PLL_EN			; Activate PLL
> 	movlw   0x40
>          movwf   OSCTUNE, A
> #endif
>
> To activate it, place the next line in 18f-main.cfg :
>
> #define PLL_EN	\ Activate PLL from SW
>
> I suggest to build this modifications in the FF.
>
> BR
> Attila Herman
>
>
>
>
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