Re: [Flashforth-devel] FF 3.8 onto newer PIC18FxxK22 chips

[Mikael N. <mik...@pp...>]

Craig,
please reply to the list. Others may have some input also.

If the ms-timer interrupts are not firing and you have idle mode in use
there will be watchdog resets occuring. That could explain some of your 
problems.

How should the timers be configured to use the internal clock as source 
on these chips ?

BR Mike

On 09/16/2013 11:34 PM, craig bair wrote:
> Mike,
>
> OSCCON wants to be 0xF0 and OSCTUNE wants PLLEN set (0x40)... OSCCON2 is fine on default.
> I went a few rounds with the PLL before finding out that it only works with Primary Clock Selected.
>
> That setup was what drove me to tinker with the .ASM file.  Well, that and the need to go into 16-bit BRG mode to get the UART into the right range.
>
> CONFIG BITS:
>      config FOSC = INTIO67    ;Internal oscillator block
> ;    config FOSC = ECMPIO6    ;EC oscillator (medium power, 500 kHz-16 MHz)
> ; Note: PLL only operates with PRIMARY CLOCK
>      config PLLCFG = ON        ;Oscillator multiplied by 4
>      config PRICLKEN = ON    ;Primary clock enabled
>      config FCMEN = OFF        ;Fail-Safe Clock Monitor disabled
>      config IESO = OFF        ;Oscillator Switchover mode disabled
>      config PWRTEN= OFF ;ON        ;Power up timer enabled
>      config BOREN = OFF        ;Brown-out Reset disabled in hardware and software
>      config BORV = 285        ;VBOR set to 2.85 V nominal
>      config WDTEN = ON        ;WDT is always enabled. SWDTEN bit has no effect
>      config WDTPS = 256        ;Watchdog Timer Postscale
> ; CCP2 MUX bit:
> ;    config CCP2MX = PORTB3    ;CCP2 input/output is multiplexed with RB3
>      config CCP2MX = PORTC1    ;CCP2 input/output is multiplexed with RC1
>      config PBADEN = OFF        ;PORTB<5:0> pins are configured as digital I/O on Reset
> ; P3A/CCP3 Mux bit:
> ;    config CCP3MX = PORTC6    ;P3A/CCP3 input/output is mulitplexed with RC6
> ;    config CCP3MX = PORTB5    ;P3A/CCP3 input/output is multiplexed with RB5
>      config HFOFST = OFF        ;HFINTOSC output and ready status are delayed by the oscillator stable status
> ; Timer3 Clock input mux bit:
> ;    config T3CMX = PORTB5    ;T3CKI is on RB5
> ;    config T3CMX = PORTC0    ;T3CKI is on RC0
> ; ECCP2 B output mux bit:
> ;    config P2BMX = PORTC0    ;P2B is on RC0
> ;    config P2BMX = PORTB5    ;P2B is on RB5
>      config MCLRE = EXTMCLR    ;MCLR pin enabled, RE3 input pin disabled
>      config STVREN = ON        ;Stack full/underflow will cause Reset
>      config LVP = OFF        ;Single-Supply ICSP disabled
>      config XINST = OFF        ;Instruction set extension and Indexed Addressing mode disabled
>      config DEBUG = OFF        ;Background Debug disabled
>
>
>
> The SIM is dicey for the PIC18FxxK22 chips and may not get fixed with the new MPLab-X takeover.  I'm still running XP single-core machines, so I really can't afford the processor overhead of JAVA-based software.  At least not until the economy picks up again.
>
> what I DID stumble across building up pieces and running test routines on the chip was that the ms-timer interrupts weren't firing.  I've gone back into the docs for TMR3 and there are different bit-settings for timer osc inputs and the original takes it off the external pin.  I'm switching it to System Clock (Fosc) and I'll see what that does.
>
> Thanks for the comments/suggestions, I'm pretty isolated and don't get to chat with programmers often.
>
> craig
>
> ...not a speck of serial...
>