pll clock change on dspic33ck64mc105

[ronny suy]

Hi
I received my dspic nano board some days ago , succesfully compiled and installed FF5.
Now my question ; looking into the code I noticed that it runs on 75Mips , but according to the datasheet it should be able to run at 100Mips (100Mhz)
I tried several things to accomplish this , but the baudrate of the serial port isn't 115200 anymore. (last attempt it was only about 75000 baud.

I changed this :
.equ FREQ_OSC, 150000000 ; 75 MIPS FNOSC=FRCPLL and default PLL values
to
.equ FREQ_OSC, 200000000 ; 75 MIPS FNOSC=FRCPLL and default PLL values

and added this after ifndecl __dsPIC30F

.ifndecl __dsPIC30F
mov #0x00c8,w0 ;equals 200 for pll feedback divider (instead of 150 as default)
mov w0,pllfbd
mov #0x0042,w0 ;postdiv1=4 , postdiv2=2
mov w0,plldiv
mov.b OSCCONH, WREG ; continue with existing code from here
...

     IMHO this should result in a pll of 8MHz*200 = 1600MHz
     divided by 8 (postdiv1*postdiv2) result in 1600/8 = 200MHz
         which divided by 2 (fixed) gives a Fcy of 100Mhz.

If programming this , I see the board resetting but with a wrong baudrate.
I assume somewhere I made a mistake , but I don't exacly know where.
Can someone help me on this please.

Kind regards,
Ronny

[Mikael Nordman]

You have to startup in FRC mode, not FRCPLL mode. And then do the clock switch according to example 9.2 in the datasheet. The clock switch part is missing from the FF code.

From the data sheet:

Note:
The PLL Phase Detector Input Divider Select (PLLPREx) bits and the PLL Feedback Divider (PLLFBDIVx)
bits should not be changed when operating in PLL mode. Therefore, the user must start in either a non-
PLL mode or clock switch to a non-PLL mode (e.g., internal FRC Oscillator) to make any necessary
changes and then clock switch to the desired PLL mode.
It is not permitted to directly clock switch from one PLL clock source to a different PLL clock source. The
user would need to transition between PLL clock sources with a clock switch to a non-PLL clock source.

//code example for 50 MIPS system clock using 8MHz FRC
// Select Internal FRC at POR
_FOSCSEL(FNOSC_FRC & IESO_OFF);
// Enable Clock Switching
_FOSC(FCKSM_CSECMD);
int main()
{
// Configure PLL prescaler, both PLL postscalers, and PLL feedback divider
CLKDIVbits.PLLPRE = 1;
// N1=1
PLLFBDbits.PLLFBDIV = 125;
// M = 125
PLLDIVbits.POST1DIV = 5;
// N2=5
PLLDIVbits.POST2DIV = 1;
// N3=1
// Initiate Clock Switch to FRC with PLL (NOSC=0b001)
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur
while (OSCCONbits.OSWEN!= 0);
// Wait for PLL to lock
while (OSCCONbits.LOCK!= 1);
}

[ronny suy]

Hi Mikael ,

Thanks for the info.
With this I succeeded in running the controller at 100Mhz
This is the code : changed from line 893 on

.ifndecl __dsPIC30F
; Ronny ; attempt to switch the controller to 100Mhz
bclr TRISD, #10 ;to be sure the program comes to this point
bclr PORTD, #10 ;this lights the onboard led
mov #PLLFBD,W0 ;Set 'M' to 200
mov #200,W1 ;Other values pll related stay at default
mov W1,[W0]
;Unlock oscconh and write 0x01
mov.b #0x78,W1
mov.b #0x9a,W2
mov.b #0x01,W3
mov #OSCCONH, W0
mov.b W1,[W0]
mov.b W2,[W0]
mov.b W3,[W0]
;Unlock oscconl and write 0x01 to request osc change
mov.b #0x46,W1
mov.b #0x57,W2
mov.b #0x01,W3
mov #OSCCONL, W0
mov.b W1,[W0]
mov.b W2,[W0]
mov.b W3,[W0]
;Wait for the switch to complete
WAITFORSWITCH:
btsc OSCCON, #0 ; OSWEN
bra WAITFORSWITCH
;Wait for the pll to be locked
WAITFORLOCK:
btss OSCCON, #5 ; LOCK
bra WAITFORLOCK

This is commented !
; mov.b OSCCONH, WREG
; and #7, W0
; cp W0, #1
; bra z, PLL_IN_USE
; cp W0, #3
; bra nz, PLL_NOT_IN_USE
;PLL_IN_USE:
;.ifdef PLL_FBD
; mov #PLL_FBD, W0
; mov W0, PLLFBD
.endif
;WAITFORLOCK:
; btss OSCCON, #5;LOCK
; bra WAITFORLOCK
;PLL_NOT_IN_USE:
;.endif

Also changed line 3 of p33ck_config.inc :

.equ FREQ_OSC, 200000000 ; 100 MIPS FNOSC=FRCPLL and adjusted pll values

Baudrate is now back 115200 as it should.

Regards,
Ronny

[ronny suy]

Oh and some fuses are also changed :

// FOSCSEL
pragma config FNOSC = FRC // Oscillator Source Selection (Internal Fast RC (FRC))
pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FOSC
pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
pragma config FCKSM = CSECME // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are enabled)
pragma config PLLKEN = ON // PLL Lock Enable (PLL clock output will be disabled if LOCK is lost)
pragma config XTCFG = G3 // XT Config (24-32 MHz crystals)
pragma config XTBST = ENABLE // XT Boost (Boost the kick-start)