Re: [E-devel] Re: Patches to Eterm

[Tres M. <tr...@mi...>]

Damn.  I sent this privately to Mike because I forgot to change the
address.  I don't know why some people's email leaves out the list but
sorry Mike.  For the list:

On Thu, 2005-06-16 at 13:33 -0400, Mike Frysinger wrote:
> On Tuesday 14 June 2005 11:50 pm, Edward Presutti wrote:
> > Is it possible to enable Eterm's SSE2 support on P4 class processors? I've
> > got a Northwood class P4 3.2 w/ SSE2, but the new makefile looks for
> > X86_64 architecture to determine whether or not to enable SSE2. Is this
> > patch specific to the X86_64 architecture or will it work on P4 class
> > processors?
> 
> the autotool checks are only used in the default case where the user doesnt 
> say whether they want sse2
> 
> you can simply run `./configure --enable-sse2` on your machine
> -mike

The only thing that will enable on a Northwood core is an assembler
error on the first quad-word instruction, leaq.  (See my previous
email.)  If it does assemble then it will throw an "invalid op code"
exception when executed.  I would be willing to port the pure assembly
stuff, mmx_cmod.S, to SSE for 32 bit if someone would be willing to test
it as my dual PII doesn't have SSE.  I have received a couple of private
emails regarding this as well.  That is provided that MeJ won't get
annoyed at a fourth implementation that does the same thing.  It should
be twice as fast as the MMX/32 one though.

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-- 
Tres