From: <jmk...@at...> - 2003-10-22 22:06:08
|
Abdul wrote: > I have designed a simple stepper pulse generator(divide by N type). > the output is described as: > > fout(in kHz) = (1000 / ((N + 1) x 2) ) x Clock (in Mhz) > > the counter is16bit. 65535 >= N >= 1 > > with a 500khz clock, fout min is 3.8Hz, and fout max is 125Khz. > with 1 Mhz clock, fout min is 7.6Hz and max is 250khz. > > Is there a requirement of step rates below 3.8Hz or 7.6Hz in any > application? I dont think stepper motors work at very low step > rates, but I may be wrong. > > I could only fit 5 step generators in the fpga with all the I/O > and encoder counters. I hope that will be enough for most applications. > This is why I don't like divide by N step pulse generators... First, a simple answer to your question - yes, you do need frequencies below a few Hz, all the way down to zero hz. However that doesn't mean your circuit won't work. The servo loop can alternate between two different output frequencies so that the average rate is the one you want. You _must_ have a way to output zero Hz though. With a divide by N circuit, that means special logic to detect whatever divider value you want to use for zero Hz and stop the clock when it is detected. The second problem is at the high end. Yes, your highest frequency might be 125KHz, but your next highest is 83.333KHz, and the one after that is 65.5KHz. Those are pretty big steps. And they are at the high frequency end of the range, which is where the motor will be most sensitive to large jumps. I much prefer a method known as direct digital synthesis. We used it in the early 90's in an AC drive, and it has been used elsewhere both before and since then. Mariss from Geckodrive is using it in his G2002, and the following is snipped from his description on the Geckodrives Yahoo group (he writes better than I do): > You are probably familiar with the usual method of generating > frequencies; load a value into a counter, have it count down > to zero, output a pulse, re-load the value an so on. As an > example, say you load a down-counter (decimal) with "9" and > clock it at 1 MHz. The counter would count down 9, 8, 7, 6, > 5, 4, 3, 2, 1, 0, output a pulse on the "0" count, re-load > with "9", count down again, and so on. The frequency would > be 10 counts at 1 uS each for a frequency of 100 kHz. > > The next higher frequency at your disposal would be to load > the counter with "8". This would result in a period of 9 uS > (8, 7, 6, 5, 4, 3, 2, 1, 0) and a frequency of 111 kHz. Your > frequency would have increased 11 kHz. > > Now let's look at the top end. The highest frequency would be > to load the counter with "0". You would then have a frequency > of 1 MHz (an output pulse for every clock cycle). Now how > about the next highest frequency, which would be to load the > counter with a "1". The sequence now would be 1, 0, 1,0 etc. > The period of course be 2 uS for a frequency of 500 kHz. That > is a frequency change of 500 kHz. So what is wrong with this > picture? Well, at the low end, an increment of period broduces > an 11 kHz change while at the high end the same increment of > change results in a 500 kHz change! This is non-linear (1/X) > and terrible! He doesn't mention that the divider can't produce zero output frequency without additional logic, but that is another disadvantage. > Now let's try it a different way. > > Let's take an adder (single digit, decimal). It has two inputs > (A) and (B) , and two outputs, (A+B) and carry. Take the output > (A+B) to the input of a clocked storage element that stores the > (A+B) output on every clock pulse (still 1 uS). The output of > the storage element feeds back to the adder's (B) input. Now > let's see what happens on each clock pulse if the (A) input > is "1" and the storage element initially outs a "0". NC will > mean "no carry" while the output pulse will occur on "carry", > or C. > > 1+0=1 NC, 1+1=2 NC, 2+1=3 NC, ... 8+1=9 NC, 9+1=0 and a C, > 1+0=1 NC, 1+1=2 NC, etc. > > There will be a "C" every tenth clock pulse for a frequency > of 100 kHz. > Now make the value on (A) equal to 2 (next highest frequency) > and see what happens. > > 2+0=2 NC, 2+2=4 NC, 4+2=6 NC, 6+2=8 NC, 8+2=0 C, 0+2=2 NC, etc. > > There will be a "carry" every 5 clock cycles for a frequency > of 200 kHz, or a 100 kHz change. Now how about what happens > at the high frequency end? The biggest number we have available > is "9", so let's use it. > > 9+0=9 NC, 9+9=8 C, 9+8=7 C. .... 9+2=1 C, 9+1=0 C, > 9+0=9 NC, 9+9=8 C, etc. > > What we have now is 9 output pulses for every clock cycles for a > frequency of 9/10 of 1 MHz, or 900 kHz. > > If we replace (A) with "8", we will get 8 "carrys" for every 10 > clock cycles for a frequency of 800 kHz. Well, this is much better; > we have an increment of frequency change produce an equal change > (100 kHz) in frequency. Now the relationship between frequency > command ( A input) and frequency is linear, i.e. the change in > frequency per command increment is independent of frequency range. If (A) is zero, the adder will not change, and an output frequency of zero Hz is created, with no special logic. The G2002 actually uses 16 bit binary counters, not a single digit decimal counter as described above, but the results are the same. Possible output frequencies are evenly distributed over the entire range from (and including) zero, to the clock frequency. There is a jitter of one clock period in the output, which can be addressed by raising the clock frequency and using a post divider. I strongly encourage you to at least look at this method of making step pulses before you commit to divide-by-N. Regards, John Kasunich |