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[Emc-commit] master: Rename the Hostmot2 DPLL function to be consistent with other modules.
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From: Andy P. <gi...@gi...> - 2013-10-31 01:40:36
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Rename the Hostmot2 DPLL function to be consistent with other modules. Signed-off-by: Andy Pugh <an...@bo...> http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=ac64b2d --- docs/man/man9/hostmot2.9 | 28 ++-- src/Makefile | 2 +- src/hal/drivers/mesa-hostmot2/abs_encoder.c | 2 +- src/hal/drivers/mesa-hostmot2/dpll.c | 250 ++++++++++++++++++++++++++++ src/hal/drivers/mesa-hostmot2/hm2_dpll.c | 250 ---------------------------- src/hal/drivers/mesa-hostmot2/hostmot2.c | 17 +- src/hal/drivers/mesa-hostmot2/hostmot2.h | 24 +-- src/hal/drivers/mesa-hostmot2/pins.c | 2 +- 8 files changed, 287 insertions(+), 288 deletions(-) diff --git a/docs/man/man9/hostmot2.9 b/docs/man/man9/hostmot2.9 index cb3b55b..806be9c 100644 --- a/docs/man/man9/hostmot2.9 +++ b/docs/man/man9/hostmot2.9 @@ -119,9 +119,9 @@ for F might be "hm2/5i20/SVST8_4.BIT". The hostmot2 firmware files are supplied by the hostmot2-firmware packages, available from linuxcnc.org. .RE .TP -\fBnum_hm2_dplls\fR [optional, default: -1] -The hm2_dpll is a phase-locked loop timer module which may be used to trigger -certain types of encoder. This parameter can be used to disable the hm2_dpll by +\fBnum_dplls\fR [optional, default: -1] +The hm2dpll is a phase-locked loop timer module which may be used to trigger +certain types of encoder. This parameter can be used to disable the hm2dpll by setting the number to 0. There is only ever one module of this type, with 4 timer channels, so the other valid numbers are -1 (enable all) and 1, both of which end up meaning the same thing. @@ -200,8 +200,8 @@ If specified, this turns on a raw access mode, whereby a user can peek and poke the firmware from HAL. See Raw Mode below. .RE -.SH hm2dpll -The hm2_dpll module has pins like "hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll\fR" +.SH dpll +The hm2dpll module has pins like "hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll\fR" It is likely that the pin-count will decrease in the future and that some pins will become parameters. This module is a phase-locked loop that will synchronise itself with the thread @@ -213,7 +213,7 @@ as fresh as possible. Pins: .TP -(float, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.NN.timer-us +(float, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.NN.timer-us This pin sets the triggering offset of the associated timer. There are 4 timers numbered 01 to 04, represented by the NN digits in the pin name. The units are micro-seconds. Negative numbers indicate that the trigger should @@ -227,28 +227,28 @@ until errors appear, and for very long bit-length or slow encoders it will need to be increased. .TP -(float, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.base-freq-khz +(float, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.base-freq-khz This pin sets the base frequency of the phase-locked loop. by default it will be set to the nominal frequency of the thread in which the PLL is running and wil not normally need to be changed. .TP -(float, out) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.phase-error-us +(float, out) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.phase-error-us Indicates the phase eror of the DPLL. If the number cycles by a large amount it is likely that the PLL has failed to achieve lock and adjustments will need to be made. .TP -(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.time-const" +(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.time-const" The filter time-constant for the PLL. Default 40960 (0xA000) .TP -(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.plimit" +(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.plimit" Sets the phase adjustment limit of the PLL. If the value is zero then the PLL will free-run at the base frequency independent of the servo thread rate. This is probably not what you want. Default 4194304 (0x400000) Units not known... .TP -(u32, out) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.ddsize +(u32, out) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.ddsize Used internally by the driver, likely to disappear. .TP -(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.hm2dpll.prescale +(u32, in) hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.dpll.prescale Prescale factor for the rate generator. Default 1. @@ -456,7 +456,7 @@ a clock frequency of 500,000 Hz. .TP (u32 r/w) hm2_XiXX.N.ssi.MM.timer-num This parameter allocates the SSI module to a specific hm2dpll timer instance. -This pin is only of use in firmwares which contain a hm2_dpll function and will +This pin is only of use in firmwares which contain a hm2dpll function and will default to 1 in cases where there is such a function, and 0 if there is not. The pin can be used to disable reads of the encoder, by setting to a nonexistent timer number, or to 0. @@ -1140,7 +1140,7 @@ EPP bus.) fBhm2_\fI<BoardType>\fB.\fI<BoardNum>\fB.trigger-encoders\fR This function will only appear if the firmware contains a BiSS, Fanuc or SSI encoder module and if the firmare does not contain a hm2dpll -module (qv) or if the modparam contains num_hm2_dplls=0. +module (qv) or if the modparam contains num_dplls=0. This function should be inserted first in the thread so that the encoder data is ready when the main \fBhm2_XiXX.NN.read\fR function runs. An error message will be printed if the encoder read is not finished in time. It may be possible to diff --git a/src/Makefile b/src/Makefile index 7bb27ba..3be7551 100755 --- a/src/Makefile +++ b/src/Makefile @@ -777,7 +777,7 @@ hostmot2-objs := \ hal/drivers/mesa-hostmot2/uart.o \ hal/drivers/mesa-hostmot2/watchdog.o \ hal/drivers/mesa-hostmot2/pins.o \ - hal/drivers/mesa-hostmot2/hm2_dpll.o \ + hal/drivers/mesa-hostmot2/dpll.o \ hal/drivers/mesa-hostmot2/led.o \ hal/drivers/mesa-hostmot2/tram.o \ hal/drivers/mesa-hostmot2/raw.o \ diff --git a/src/hal/drivers/mesa-hostmot2/abs_encoder.c b/src/hal/drivers/mesa-hostmot2/abs_encoder.c index 8b381f1..91c4cf5 100644 --- a/src/hal/drivers/mesa-hostmot2/abs_encoder.c +++ b/src/hal/drivers/mesa-hostmot2/abs_encoder.c @@ -130,7 +130,7 @@ int hm2_absenc_register_tram(hostmot2_t *hm2){ // If there is no dpll to link to, then we export the trigger function. - if (hm2->config.num_hm2dplls == 0){ + if (hm2->config.num_dplls == 0){ char name[HM2_SSERIAL_MAX_STRING_LENGTH+1] = ""; rtapi_snprintf(name, sizeof(name), "%s.trigger-encoders", hm2->llio->name); diff --git a/src/hal/drivers/mesa-hostmot2/dpll.c b/src/hal/drivers/mesa-hostmot2/dpll.c new file mode 100644 index 0000000..54dfad2 --- /dev/null +++ b/src/hal/drivers/mesa-hostmot2/dpll.c @@ -0,0 +1,250 @@ + +// +// Copyright (C) 2013 Andy Pugh + +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +// + +// A driver for the Hostmot2 HM2_DPLL module that allows pre-triggering of some +// other modules. + + +#include <linux/slab.h> + +#include "rtapi.h" +#include "rtapi_string.h" +#include "rtapi_math.h" + +#include "hal.h" + +#include "hal/drivers/mesa-hostmot2/hostmot2.h" + +int hm2_dpll_parse_md(hostmot2_t *hm2, int md_index) { + + hm2_module_descriptor_t *md = &hm2->md[md_index]; + int r; + + // + // some standard sanity checks + // + + if (!hm2_md_is_consistent_or_complain(hm2, md_index, 0, 7, 4, 0x0000)) { + HM2_ERR("inconsistent Module Descriptor!\n"); + return -EINVAL; + } + + + if (hm2->config.num_dplls == 0) return 0; + + if (hm2->config.num_dplls > md->instances) { + hm2->dpll.num_instances = md->instances; + HM2_ERR( "There are only %d dplls on this board type, using %d\n", + md->instances, md->instances ); + } else if (hm2->config.num_dplls == -1) { + hm2->dpll.num_instances = md->instances; + } else hm2->dpll.num_instances = hm2->config.num_dplls; + + // + // looks good, start initializing + // + + hm2->dpll.clock_frequency = md->clock_freq; + hm2->dpll.base_rate_addr = md->base_address + 0 * md->register_stride; + hm2->dpll.phase_err_addr = md->base_address + 1 * md->register_stride; + hm2->dpll.control_reg0_addr = md->base_address + 2 * md->register_stride; + hm2->dpll.control_reg1_addr = md->base_address + 3 * md->register_stride; + hm2->dpll.timer_12_addr = md->base_address + 4 * md->register_stride; + hm2->dpll.timer_34_addr = md->base_address + 5 * md->register_stride; + hm2->dpll.hm2_dpll_sync_addr = md->base_address + 6 * md->register_stride; + + // export to HAL + hm2->dpll.pins = hal_malloc(sizeof(hm2_dpll_pins_t)); + + r = hal_pin_float_newf(HAL_IN, &(hm2->dpll.pins->time1_us), + hm2->llio->comp_id, "%s.dpll.01.timer-us", hm2->llio->name); + r += hal_pin_float_newf(HAL_IN, &(hm2->dpll.pins->time2_us), + hm2->llio->comp_id, "%s.dpll.02.timer-us", hm2->llio->name); + r += hal_pin_float_newf(HAL_IN, &(hm2->dpll.pins->time3_us), + hm2->llio->comp_id, "%s.dpll.03.timer-us", hm2->llio->name); + r += hal_pin_float_newf(HAL_IN, &(hm2->dpll.pins->time4_us), + hm2->llio->comp_id, "%s.dpll.04.timer-us", hm2->llio->name); + r += hal_pin_float_newf(HAL_IN, &(hm2->dpll.pins->base_freq), + hm2->llio->comp_id, "%s.dpll.base-freq-khz", hm2->llio->name); + r += hal_pin_float_newf(HAL_OUT, &(hm2->dpll.pins->phase_error), + hm2->llio->comp_id, "%s.dpll.phase-error-us", hm2->llio->name); + r += hal_pin_u32_newf(HAL_IN, &(hm2->dpll.pins->time_const), + hm2->llio->comp_id, "%s.dpll.time-const", hm2->llio->name); + r += hal_pin_u32_newf(HAL_IN, &(hm2->dpll.pins->plimit), + hm2->llio->comp_id, "%s.dpll.plimit", hm2->llio->name); + r += hal_pin_u32_newf(HAL_OUT, &(hm2->dpll.pins->ddssize), + hm2->llio->comp_id, "%s.dpll.ddsize", hm2->llio->name); + r += hal_pin_u32_newf(HAL_OUT, &(hm2->dpll.pins->prescale), + hm2->llio->comp_id, "%s.dpll.prescale", hm2->llio->name); + if (r < 0) { + HM2_ERR("error adding hm2_dpll timer pins, Aborting\n"); + goto fail0; + } + *hm2->dpll.pins->time1_us = 100.0; + *hm2->dpll.pins->time2_us = 100.0; + *hm2->dpll.pins->time3_us = 100.0; + *hm2->dpll.pins->time4_us = 100.0; + *hm2->dpll.pins->prescale = 1; + *hm2->dpll.pins->base_freq = -1; // An indication it needs init + *hm2->dpll.pins->time_const = 0xA000; + *hm2->dpll.pins->plimit = 0x400000; + + r = hm2_register_tram_read_region(hm2, hm2->dpll.hm2_dpll_sync_addr, + sizeof(u32), &hm2->dpll.hm2_dpll_sync_reg); + if (r < 0) { + HM2_ERR("Error registering tram synch write. Aborting\n"); + goto fail0; + } + r = hm2_register_tram_read_region(hm2, hm2->dpll.control_reg1_addr, + sizeof(u32), &hm2->dpll.control_reg1_read); + if (r < 0) { + HM2_ERR("Error registering dpll control reg 1. Aborting\n"); + goto fail0; + } + + return hm2->dpll.num_instances; + + fail0: + return r; + +} + +void hm2_dpll_process_tram_read(hostmot2_t *hm2, long period){ + hm2_dpll_pins_t *pins; + + if (hm2->dpll.num_instances == 0) return; + + pins = hm2->dpll.pins; + + *pins->phase_error = (s32)*hm2->dpll.hm2_dpll_sync_reg + * (period / 4294967296000.00) ; + *pins->ddssize = *hm2->dpll.control_reg1_read & 0xFF; +} + +void hm2_dpll_write(hostmot2_t *hm2, long period) { + hm2_dpll_pins_t *pins; + double period_ms = period / 1000; + u32 buff; + static int init_counter = 0; + + if (hm2->dpll.num_instances == 0) return; + + if (init_counter < 100){ + init_counter++; + buff = 0; // Force phase error to zero at startup + hm2->llio->write(hm2->llio, + hm2->dpll.phase_err_addr, + &buff, + sizeof(u32)); + hm2->dpll.control_reg0_written= buff; + } + + pins = hm2->dpll.pins; + + if (*pins->base_freq < 0 ) { + *pins->base_freq = 1000.0/period_ms; + } + + *pins->prescale = (0x40000000LL * hm2->dpll.clock_frequency) + / ((1LL << *pins->ddssize) * *pins->base_freq * 1000.0); + + if (*pins->prescale < 1) *pins->prescale = 1; + + buff = (u32)((*pins->base_freq * 1000.0 + * (1LL << *pins->ddssize) + * *pins->prescale) + / hm2->dpll.clock_frequency); + + if (buff != hm2->dpll.base_rate_written){ + hm2->llio->write(hm2->llio, + hm2->dpll.base_rate_addr, + &buff, + sizeof(u32)); + hm2->dpll.base_rate_written= buff; + } + buff = (u32)(*pins->prescale << 24 + | *pins->plimit); + if (buff != hm2->dpll.control_reg0_written){ + hm2->llio->write(hm2->llio, + hm2->dpll.control_reg0_addr, + &buff, + sizeof(u32)); + hm2->dpll.control_reg0_written= buff; + } + buff = (u32)(*pins->time_const << 16); + if (buff != hm2->dpll.control_reg1_written){ + hm2->llio->write(hm2->llio, + hm2->dpll.control_reg1_addr, + &buff, + sizeof(u32)); + hm2->dpll.control_reg1_written= buff; + } + buff = (u32)((-*hm2->dpll.pins->time2_us / period_ms) * 0x10000) << 16 + | (u32)((-*hm2->dpll.pins->time1_us / period_ms) * 0x10000); + if (buff != hm2->dpll.timer_12_written){ + hm2->llio->write(hm2->llio, + hm2->dpll.timer_12_addr, + &buff, + sizeof(u32)); + hm2->dpll.timer_12_written = buff; + } + buff = (u32)((-*hm2->dpll.pins->time4_us / period_ms) * 0x10000) << 16 + | (u32)((-*hm2->dpll.pins->time3_us / period_ms) * 0x10000); + if (buff != hm2->dpll.timer_34_written){ + hm2->llio->write(hm2->llio, + hm2->dpll.timer_34_addr, + &buff, + sizeof(u32)); + hm2->dpll.timer_34_written = buff; + } +} + +int hm2_dpll_force_write(hostmot2_t *hm2) { + int i; + if (hm2->dpll.num_instances == 0) return 0; + for (i = 0; i < hm2->absenc.num_chans; i ++){ + hm2_sserial_remote_t *chan = &hm2->absenc.chans[i]; + switch (chan->myinst){ + case HM2_GTAG_SSI: + chan->params->timer_num = 1; + break; + case HM2_GTAG_BISS: + if (hm2->dpll.num_instances > 1){ + chan->params->timer_num = 2; + } else { + chan->params->timer_num = 1; + } + break; + case HM2_GTAG_FABS: + if (hm2->dpll.num_instances > 2){ + chan->params->timer_num = 3; + } else { + chan->params->timer_num = 1; + } + break; + } + /* Other triggerable component types should be added here */ + } + return 0; +} + + +void hm2_dpll_cleanup(hostmot2_t *hm2) { + // Should all be handled by the HAL housekeeping +} diff --git a/src/hal/drivers/mesa-hostmot2/hm2_dpll.c b/src/hal/drivers/mesa-hostmot2/hm2_dpll.c deleted file mode 100644 index 169d692..0000000 --- a/src/hal/drivers/mesa-hostmot2/hm2_dpll.c +++ /dev/null @@ -1,250 +0,0 @@ - -// -// Copyright (C) 2013 Andy Pugh - -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -// - -// A driver for the Hostmot2 HM2_DPLL module that allows pre-triggering of some -// other modules. - - -#include <linux/slab.h> - -#include "rtapi.h" -#include "rtapi_string.h" -#include "rtapi_math.h" - -#include "hal.h" - -#include "hal/drivers/mesa-hostmot2/hostmot2.h" - -int hm2_hm2dpll_parse_md(hostmot2_t *hm2, int md_index) { - - hm2_module_descriptor_t *md = &hm2->md[md_index]; - int r; - - // - // some standard sanity checks - // - - if (!hm2_md_is_consistent_or_complain(hm2, md_index, 0, 7, 4, 0x0000)) { - HM2_ERR("inconsistent Module Descriptor!\n"); - return -EINVAL; - } - - - if (hm2->config.num_hm2dplls == 0) return 0; - - if (hm2->config.num_hm2dplls > md->instances) { - hm2->hm2dpll.num_instances = md->instances; - HM2_ERR( "There are only %d dplls on this board type, using %d\n", - md->instances, md->instances ); - } else if (hm2->config.num_hm2dplls == -1) { - hm2->hm2dpll.num_instances = md->instances; - } else hm2->hm2dpll.num_instances = hm2->config.num_hm2dplls; - - // - // looks good, start initializing - // - - hm2->hm2dpll.clock_frequency = md->clock_freq; - hm2->hm2dpll.base_rate_addr = md->base_address + 0 * md->register_stride; - hm2->hm2dpll.phase_err_addr = md->base_address + 1 * md->register_stride; - hm2->hm2dpll.control_reg0_addr = md->base_address + 2 * md->register_stride; - hm2->hm2dpll.control_reg1_addr = md->base_address + 3 * md->register_stride; - hm2->hm2dpll.timer_12_addr = md->base_address + 4 * md->register_stride; - hm2->hm2dpll.timer_34_addr = md->base_address + 5 * md->register_stride; - hm2->hm2dpll.hm2_hm2dpll_sync_addr = md->base_address + 6 * md->register_stride; - - // export to HAL - hm2->hm2dpll.pins = hal_malloc(sizeof(hm2_hm2dpll_pins_t)); - - r = hal_pin_float_newf(HAL_IN, &(hm2->hm2dpll.pins->time1_us), - hm2->llio->comp_id, "%s.hm2dpll.01.timer-us", hm2->llio->name); - r += hal_pin_float_newf(HAL_IN, &(hm2->hm2dpll.pins->time2_us), - hm2->llio->comp_id, "%s.hm2dpll.02.timer-us", hm2->llio->name); - r += hal_pin_float_newf(HAL_IN, &(hm2->hm2dpll.pins->time3_us), - hm2->llio->comp_id, "%s.hm2dpll.03.timer-us", hm2->llio->name); - r += hal_pin_float_newf(HAL_IN, &(hm2->hm2dpll.pins->time4_us), - hm2->llio->comp_id, "%s.hm2dpll.04.timer-us", hm2->llio->name); - r += hal_pin_float_newf(HAL_IN, &(hm2->hm2dpll.pins->base_freq), - hm2->llio->comp_id, "%s.hm2dpll.base-freq-khz", hm2->llio->name); - r += hal_pin_float_newf(HAL_OUT, &(hm2->hm2dpll.pins->phase_error), - hm2->llio->comp_id, "%s.hm2dpll.phase-error-us", hm2->llio->name); - r += hal_pin_u32_newf(HAL_IN, &(hm2->hm2dpll.pins->time_const), - hm2->llio->comp_id, "%s.hm2dpll.time-const", hm2->llio->name); - r += hal_pin_u32_newf(HAL_IN, &(hm2->hm2dpll.pins->plimit), - hm2->llio->comp_id, "%s.hm2dpll.plimit", hm2->llio->name); - r += hal_pin_u32_newf(HAL_OUT, &(hm2->hm2dpll.pins->ddssize), - hm2->llio->comp_id, "%s.hm2dpll.ddsize", hm2->llio->name); - r += hal_pin_u32_newf(HAL_OUT, &(hm2->hm2dpll.pins->prescale), - hm2->llio->comp_id, "%s.hm2dpll.prescale", hm2->llio->name); - if (r < 0) { - HM2_ERR("error adding hm2_dpll timer pins, Aborting\n"); - goto fail0; - } - *hm2->hm2dpll.pins->time1_us = 100.0; - *hm2->hm2dpll.pins->time2_us = 100.0; - *hm2->hm2dpll.pins->time3_us = 100.0; - *hm2->hm2dpll.pins->time4_us = 100.0; - *hm2->hm2dpll.pins->prescale = 1; - *hm2->hm2dpll.pins->base_freq = -1; // An indication it needs init - *hm2->hm2dpll.pins->time_const = 0xA000; - *hm2->hm2dpll.pins->plimit = 0x400000; - - r = hm2_register_tram_read_region(hm2, hm2->hm2dpll.hm2_hm2dpll_sync_addr, - sizeof(u32), &hm2->hm2dpll.hm2_hm2dpll_sync_reg); - if (r < 0) { - HM2_ERR("Error registering tram synch write. Aborting\n"); - goto fail0; - } - r = hm2_register_tram_read_region(hm2, hm2->hm2dpll.control_reg1_addr, - sizeof(u32), &hm2->hm2dpll.control_reg1_read); - if (r < 0) { - HM2_ERR("Error registering hm2dpll control reg 1. Aborting\n"); - goto fail0; - } - - return hm2->hm2dpll.num_instances; - - fail0: - return r; - -} - -void hm2_hm2dpll_process_tram_read(hostmot2_t *hm2, long period){ - hm2_hm2dpll_pins_t *pins; - - if (hm2->hm2dpll.num_instances == 0) return; - - pins = hm2->hm2dpll.pins; - - *pins->phase_error = (s32)*hm2->hm2dpll.hm2_hm2dpll_sync_reg - * (period / 4294967296000.00) ; - *pins->ddssize = *hm2->hm2dpll.control_reg1_read & 0xFF; -} - -void hm2_hm2dpll_write(hostmot2_t *hm2, long period) { - hm2_hm2dpll_pins_t *pins; - double period_ms = period / 1000; - u32 buff; - static int init_counter = 0; - - if (hm2->hm2dpll.num_instances == 0) return; - - if (init_counter < 100){ - init_counter++; - buff = 0; // Force phase error to zero at startup - hm2->llio->write(hm2->llio, - hm2->hm2dpll.phase_err_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.control_reg0_written= buff; - } - - pins = hm2->hm2dpll.pins; - - if (*pins->base_freq < 0 ) { - *pins->base_freq = 1000.0/period_ms; - } - - *pins->prescale = (0x40000000LL * hm2->hm2dpll.clock_frequency) - / ((1LL << *pins->ddssize) * *pins->base_freq * 1000.0); - - if (*pins->prescale < 1) *pins->prescale = 1; - - buff = (u32)((*pins->base_freq * 1000.0 - * (1LL << *pins->ddssize) - * *pins->prescale) - / hm2->hm2dpll.clock_frequency); - - if (buff != hm2->hm2dpll.base_rate_written){ - hm2->llio->write(hm2->llio, - hm2->hm2dpll.base_rate_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.base_rate_written= buff; - } - buff = (u32)(*pins->prescale << 24 - | *pins->plimit); - if (buff != hm2->hm2dpll.control_reg0_written){ - hm2->llio->write(hm2->llio, - hm2->hm2dpll.control_reg0_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.control_reg0_written= buff; - } - buff = (u32)(*pins->time_const << 16); - if (buff != hm2->hm2dpll.control_reg1_written){ - hm2->llio->write(hm2->llio, - hm2->hm2dpll.control_reg1_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.control_reg1_written= buff; - } - buff = (u32)((-*hm2->hm2dpll.pins->time2_us / period_ms) * 0x10000) << 16 - | (u32)((-*hm2->hm2dpll.pins->time1_us / period_ms) * 0x10000); - if (buff != hm2->hm2dpll.timer_12_written){ - hm2->llio->write(hm2->llio, - hm2->hm2dpll.timer_12_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.timer_12_written = buff; - } - buff = (u32)((-*hm2->hm2dpll.pins->time4_us / period_ms) * 0x10000) << 16 - | (u32)((-*hm2->hm2dpll.pins->time3_us / period_ms) * 0x10000); - if (buff != hm2->hm2dpll.timer_34_written){ - hm2->llio->write(hm2->llio, - hm2->hm2dpll.timer_34_addr, - &buff, - sizeof(u32)); - hm2->hm2dpll.timer_34_written = buff; - } -} - -int hm2_hm2dpll_force_write(hostmot2_t *hm2) { - int i; - if (hm2->hm2dpll.num_instances == 0) return 0; - for (i = 0; i < hm2->absenc.num_chans; i ++){ - hm2_sserial_remote_t *chan = &hm2->absenc.chans[i]; - switch (chan->myinst){ - case HM2_GTAG_SSI: - chan->params->timer_num = 1; - break; - case HM2_GTAG_BISS: - if (hm2->hm2dpll.num_instances > 1){ - chan->params->timer_num = 2; - } else { - chan->params->timer_num = 1; - } - break; - case HM2_GTAG_FABS: - if (hm2->hm2dpll.num_instances > 2){ - chan->params->timer_num = 3; - } else { - chan->params->timer_num = 1; - } - break; - } - /* Other triggerable component types should be added here */ - } - return 0; -} - - -void hm2_hm2dpll_cleanup(hostmot2_t *hm2) { - // Should all be handled by the HAL housekeeping -} diff --git a/src/hal/drivers/mesa-hostmot2/hostmot2.c b/src/hal/drivers/mesa-hostmot2/hostmot2.c index fc70c3f..1f00a40 100644 --- a/src/hal/drivers/mesa-hostmot2/hostmot2.c +++ b/src/hal/drivers/mesa-hostmot2/hostmot2.c @@ -100,7 +100,7 @@ static void hm2_read(void *void_hm2, long period) { //UARTS need to be explicity handled by an external component hm2_tp_pwmgen_read(hm2); // check the status of the fault bit - hm2_hm2dpll_process_tram_read(hm2, period); + hm2_dpll_process_tram_read(hm2, period); hm2_raw_read(hm2); } @@ -136,7 +136,7 @@ static void hm2_write(void *void_hm2, long period) { hm2_encoder_write(hm2); // update ctrl register if needed hm2_absenc_write(hm2); // set bit-lengths and frequency hm2_resolver_write(hm2, period); // Update the excitation frequency - hm2_hm2dpll_write(hm2, period); // Update the timer phases + hm2_dpll_write(hm2, period); // Update the timer phases hm2_led_write(hm2); // Update on-board LEDs hm2_raw_write(hm2); @@ -278,7 +278,6 @@ const char *hm2_get_general_function_name(int gtag) { case HM2_GTAG_UART_RX: return "UART Receive Channel"; case HM2_GTAG_UART_TX: return "UART Transmit Channel"; case HM2_GTAG_DPLL: return "DPLL"; - case HM2_GTAG_HM2DPLL: return "Hostmot2 DPLL"; default: { static char unknown[100]; rtapi_snprintf(unknown, 100, "(unknown-gtag-%d)", gtag); @@ -346,7 +345,7 @@ static int hm2_parse_config_string(hostmot2_t *hm2, char *config_string) { hm2->config.num_stepgens = -1; hm2->config.num_bspis = -1; hm2->config.num_uarts = -1; - hm2->config.num_hm2dplls = -1; + hm2->config.num_dplls = -1; hm2->config.num_leds = -1; hm2->config.enable_raw = 0; hm2->config.firmware = NULL; @@ -440,9 +439,9 @@ static int hm2_parse_config_string(hostmot2_t *hm2, char *config_string) { token += 9; hm2->config.num_leds = simple_strtol(token, NULL, 0); - } else if (strncmp(token, "num_hm2_dplls=", 14) == 0) { - token += 14; - hm2->config.num_hm2dplls = simple_strtol(token, NULL, 0); + } else if (strncmp(token, "num_dplls=", 10) == 0) { + token += 10; + hm2->config.num_dplls = simple_strtol(token, NULL, 0); } else if (strncmp(token, "enable_raw", 10) == 0) { hm2->config.enable_raw = 1; @@ -911,7 +910,7 @@ static int hm2_parse_module_descriptors(hostmot2_t *hm2) { break; case HM2_GTAG_HM2DPLL: - md_accepted = hm2_hm2dpll_parse_md(hm2, md_index); + md_accepted = hm2_dpll_parse_md(hm2, md_index); break; case HM2_GTAG_LED: @@ -1613,6 +1612,6 @@ void hm2_force_write(hostmot2_t *hm2) { hm2_tp_pwmgen_force_write(hm2); hm2_sserial_force_write(hm2); hm2_bspi_force_write(hm2); - hm2_hm2dpll_force_write(hm2); + hm2_dpll_force_write(hm2); } diff --git a/src/hal/drivers/mesa-hostmot2/hostmot2.h b/src/hal/drivers/mesa-hostmot2/hostmot2.h index e18a553..d1f0e15 100644 --- a/src/hal/drivers/mesa-hostmot2/hostmot2.h +++ b/src/hal/drivers/mesa-hostmot2/hostmot2.h @@ -811,12 +811,12 @@ typedef struct { hal_u32_t *ddssize; hal_u32_t *time_const; hal_u32_t *prescale; -} hm2_hm2dpll_pins_t ; +} hm2_dpll_pins_t ; typedef struct { int num_instances ; - hm2_hm2dpll_pins_t *pins ; + hm2_dpll_pins_t *pins ; u32 base_rate_addr; u32 base_rate_written; @@ -830,11 +830,11 @@ typedef struct { u32 timer_12_written; u32 timer_34_addr; u32 timer_34_written; - u32 hm2_hm2dpll_sync_addr; - u32 *hm2_hm2dpll_sync_reg; + u32 hm2_dpll_sync_addr; + u32 *hm2_dpll_sync_reg; u32 clock_frequency; -} hm2_hm2dpll_t ; +} hm2_dpll_t ; // @@ -963,7 +963,7 @@ typedef struct { int num_sserials; int num_bspis; int num_uarts; - int num_hm2dplls; + int num_dplls; char sserial_modes[4][8]; int enable_raw; char *firmware; @@ -1003,7 +1003,7 @@ typedef struct { hm2_uart_t uart; hm2_ioport_t ioport; hm2_watchdog_t watchdog; - hm2_hm2dpll_t hm2dpll; + hm2_dpll_t dpll; hm2_led_t led; hm2_raw_t *raw; @@ -1232,11 +1232,11 @@ int hm2_uart_read(char *name, unsigned char data[]); // hm2dpll functions // -void hm2_hm2dpl_cleanup(hostmot2_t *hm2); -int hm2_hm2dpll_force_write(hostmot2_t *hm2); -int hm2_hm2dpll_parse_md(hostmot2_t *hm2, int md_index); -void hm2_hm2dpll_process_tram_read(hostmot2_t *hm2, long period); -void hm2_hm2dpll_write(hostmot2_t *hm2, long period); +void hm2_dpl_cleanup(hostmot2_t *hm2); +int hm2_dpll_force_write(hostmot2_t *hm2); +int hm2_dpll_parse_md(hostmot2_t *hm2, int md_index); +void hm2_dpll_process_tram_read(hostmot2_t *hm2, long period); +void hm2_dpll_write(hostmot2_t *hm2, long period); // // watchdog functions diff --git a/src/hal/drivers/mesa-hostmot2/pins.c b/src/hal/drivers/mesa-hostmot2/pins.c index 691b3d3..87fdfa2 100644 --- a/src/hal/drivers/mesa-hostmot2/pins.c +++ b/src/hal/drivers/mesa-hostmot2/pins.c @@ -590,7 +590,7 @@ void hm2_configure_pins(hostmot2_t *hm2) { hm2_pins_allocate_all(hm2, HM2_GTAG_MUXED_ENCODER_SEL, hm2->encoder.num_instances); // and about half as many I/Os as you'd expect hm2_pins_allocate_all(hm2, HM2_GTAG_MUXED_ENCODER, (hm2->encoder.num_instances+1)/2); - hm2_pins_allocate_all(hm2, HM2_GTAG_HM2DPLL, hm2->hm2dpll.num_instances); + hm2_pins_allocate_all(hm2, HM2_GTAG_HM2DPLL, hm2->dpll.num_instances); } |