[E1000-devel] TARC.COUNT bits of 8257[12]

[Masanobu S. <ms...@ex...>]

 Hi.

 82571/82572 spec update (I have Revision 6.9, December 2014) says:

	12: TCP Segmentation Offload Operations with Both Transmit Queues Enabled

	Clarification:

	When using TCP Segmentation Offload (TSO) with both Transmit Queues
	enabled, bits 6:0 “COUNT”in the TARC0 (0x03840) and TARC1 (0x3940)
	register must be set to 1 for proper operation. Failure to set COUNT=1
	can result in the Transmit flow of the 82571/82572 halting unexpectedly.

But, netdev.c in e1000e driver says:

>         /* errata: program both queues to unweighted RR */
>         if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
>                 tarc = er32(TARC(0));
>                 tarc |= 1;
>                 ew32(TARC(0), tarc);
>                 tarc = er32(TARC(1));
>                 tarc |= 1;
>                 ew32(TARC(1), tarc);
>         }
> 
>         /* Setup Transmit Descriptor Settings for eop descriptor */
>         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;

Which is correct? The document says set "COUNT" to 1, but the code just set bit 0 only.

 Is the clarification is not related to this code?

-- 
-----------------------------------------------
                SAITOH Masanobu (ms...@ex...
                                 ms...@ne...)