[E1000-devel] tuning SMP affinity with multiqueue on igb

[Ed R. <er...@pa...>]

I'm trying to find the optimum configuration for a Xeon box with
two 82574 NICs that is doing IP routing.  I've poked around with
both irqbalance and manual settings for SMP affinity.

I found this app note at Intel's site:

  http://download.intel.com/design/network/applnots/319935.pdf

Which warns that irqbalance might not work, and has this intriguing text:

> For IP forwarding, a transmit/receive queue pair should use the
> same processor core and reduce any cache synchronization between
> different cores. This can be performed by assigning transmit and
> receive interrupts to specific cores.

But I'm not sure how to interpret the words "transmit/receive queue pair".
Are they talking about queue pairs on the same card, such as eth4-rx-0 and
eth4-tx-0, or on different cards, for the expected path of the traffic
(i.e. if traffic is coming in on eth4 and going out eth5, should I map
eth4-rx-0 and eth5-tx-0 to the same CPU)?

Also, is Hyperthreading an issue, should I pretend there are only 4 CPUs
when setting up affinities or maybe turn Hyperthreading off?
/proc/interrupts shows only four queues each for rx and tx regardless of
the state of Hyperthreading.