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drm: Branch 'main'
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From: GitLab M. <git...@ke...> - 2025-12-08 13:11:08
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include/drm/drm.h | 15 +++++
include/drm/drm_fourcc.h | 25 +++++---
include/drm/drm_mode.h | 134 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 165 insertions(+), 9 deletions(-)
New commits:
commit 1b68532f88173a67724a67b0bc4a15b4c54b2885
Author: Simon Ser <co...@em...>
Date: Thu Dec 4 11:37:24 2025 +0100
Sync headers with drm-next
Synchronize drm.h, drm_mode.h and drm_fourcc.h to drm-next.
Generated using make headers_install
Generated from drm-next branch commit 0692602defb0c273f80dec9c564ca50726404aca
Signed-off-by: Simon Ser <co...@em...>
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 3ddff73d..1666e91b 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -900,6 +900,21 @@ struct drm_get_cap {
*/
#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6
+/**
+ * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE
+ *
+ * If set to 1 the DRM core will allow setting the COLOR_PIPELINE
+ * property on a &drm_plane, as well as drm_colorop properties.
+ *
+ * Setting of these plane properties will be rejected when this client
+ * cap is set:
+ * - COLOR_ENCODING
+ * - COLOR_RANGE
+ *
+ * The client must enable &DRM_CLIENT_CAP_ATOMIC first.
+ */
+#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7
+
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index c18f1f18..4a138b5f 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -979,14 +979,20 @@ extern "C" {
* 2 = Gob Height 8, Turing+ Page Kind mapping
* 3 = Reserved for future use.
*
- * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
- * bit remapping step that occurs at an even lower level than the
- * page kind and block linear swizzles. This causes the layout of
- * surfaces mapped in those SOC's GPUs to be incompatible with the
- * equivalent mapping on other GPUs in the same system.
- *
- * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
- * 1 = Desktop GPU and Tegra Xavier+ Layout
+ * 22:22 s Sector layout. There is a further bit remapping step that occurs
+ * 26:27 at an even lower level than the page kind and block linear
+ * swizzles. This causes the bit arrangement of surfaces in memory
+ * to differ subtly, and prevents direct sharing of surfaces between
+ * GPUs with different layouts.
+ *
+ * 0 = Tegra K1 - Tegra Parker/TX2 Layout
+ * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout
+ * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout
+ * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout
+ * 4 = Reserved for future use.
+ * 5 = Reserved for future use.
+ * 6 = Reserved for future use.
+ * 7 = Reserved for future use.
*
* 25:23 c Lossless Framebuffer Compression type.
*
@@ -1001,7 +1007,7 @@ extern "C" {
* 6 = Reserved for future use
* 7 = Reserved for future use
*
- * 55:25 - Reserved for future use. Must be zero.
+ * 55:28 - Reserved for future use. Must be zero.
*/
#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
fourcc_mod_code(NVIDIA, (0x10 | \
@@ -1009,6 +1015,7 @@ extern "C" {
(((k) & 0xff) << 12) | \
(((g) & 0x3) << 20) | \
(((s) & 0x1) << 22) | \
+ (((s) & 0x6) << 25) | \
(((c) & 0x7) << 23)))
/* To grandfather in prior block linear format modifiers to the above layout,
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 1e0e02a7..cbbbfc1d 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -629,6 +629,7 @@ struct drm_mode_connector_set_property {
#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
+#define DRM_MODE_OBJECT_COLOROP 0xfafafafa
#define DRM_MODE_OBJECT_ANY 0
struct drm_mode_obj_get_properties {
@@ -846,6 +847,20 @@ struct drm_color_ctm {
__u64 matrix[9];
};
+struct drm_color_ctm_3x4 {
+ /*
+ * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
+ * (not two's complement!) format.
+ *
+ * out matrix in
+ * |R| |0 1 2 3 | | R |
+ * |G| = |4 5 6 7 | x | G |
+ * |B| |8 9 10 11| | B |
+ * |1.0|
+ */
+ __u64 matrix[12];
+};
+
struct drm_color_lut {
/*
* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
@@ -857,6 +872,125 @@ struct drm_color_lut {
__u16 reserved;
};
+/*
+ * struct drm_color_lut32
+ *
+ * 32-bit per channel color LUT entry, similar to drm_color_lut.
+ */
+struct drm_color_lut32 {
+ __u32 red;
+ __u32 green;
+ __u32 blue;
+ __u32 reserved;
+};
+
+/**
+ * enum drm_colorop_type - Type of color operation
+ *
+ * drm_colorops can be of many different types. Each type behaves differently
+ * and defines a different set of properties. This enum defines all types and
+ * gives a high-level description.
+ */
+enum drm_colorop_type {
+ /**
+ * @DRM_COLOROP_1D_CURVE:
+ *
+ * enum string "1D Curve"
+ *
+ * A 1D curve that is being applied to all color channels. The
+ * curve is specified via the CURVE_1D_TYPE colorop property.
+ */
+ DRM_COLOROP_1D_CURVE,
+
+ /**
+ * @DRM_COLOROP_1D_LUT:
+ *
+ * enum string "1D LUT"
+ *
+ * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries,
+ * packed into a blob via the DATA property. The driver's
+ * expected LUT size is advertised via the SIZE property.
+ *
+ * The DATA blob is an array of struct drm_color_lut32 with size
+ * of "size".
+ */
+ DRM_COLOROP_1D_LUT,
+
+ /**
+ * @DRM_COLOROP_CTM_3X4:
+ *
+ * enum string "3x4 Matrix"
+ *
+ * A 3x4 matrix. Its values are specified via the
+ * &drm_color_ctm_3x4 struct provided via the DATA property.
+ *
+ * The DATA blob is a float[12]:
+ * out matrix in
+ * | R | | 0 1 2 3 | | R |
+ * | G | = | 4 5 6 7 | x | G |
+ * | B | | 8 9 10 12 | | B |
+ */
+ DRM_COLOROP_CTM_3X4,
+
+ /**
+ * @DRM_COLOROP_MULTIPLIER:
+ *
+ * enum string "Multiplier"
+ *
+ * A simple multiplier, applied to all color values. The
+ * multiplier is specified as a S31.32 via the MULTIPLIER
+ * property.
+ */
+ DRM_COLOROP_MULTIPLIER,
+
+ /**
+ * @DRM_COLOROP_3D_LUT:
+ *
+ * enum string "3D LUT"
+ *
+ * A 3D LUT of &drm_color_lut32 entries,
+ * packed into a blob via the DATA property. The driver's expected
+ * LUT size is advertised via the SIZE property, i.e., a 3D LUT with
+ * 17x17x17 entries will have SIZE set to 17.
+ *
+ * The DATA blob is a 3D array of struct drm_color_lut32 with dimension
+ * length of "size".
+ * The LUT elements are traversed like so:
+ *
+ * for B in range 0..n
+ * for G in range 0..n
+ * for R in range 0..n
+ * index = R + n * (G + n * B)
+ * color = lut3d[index]
+ */
+ DRM_COLOROP_3D_LUT,
+};
+
+/**
+ * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation
+ */
+enum drm_colorop_lut3d_interpolation_type {
+ /**
+ * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL:
+ *
+ * Tetrahedral 3DLUT interpolation
+ */
+ DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL,
+};
+
+/**
+ * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs
+ */
+enum drm_colorop_lut1d_interpolation_type {
+ /**
+ * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR:
+ *
+ * Linear interpolation. Values between points of the LUT will be
+ * linearly interpolated.
+ */
+ DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR,
+};
+
/**
* struct drm_plane_size_hint - Plane size hints
* @width: The width of the plane in pixel
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