From: Sergio M. B. <se...@se...> - 2007-07-30 20:31:08
|
On Mon, 2007-07-30 at 09:09 -0700, Jesse Barnes wrote: > What hardware do you have? 00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 03) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Capabilities: [e0] Vendor Specific Information 00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) (prog-if 00 [VGA]) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0100000 (32-bit, non-prefetchable) [size=512K] Region 1: I/O ports at 2000 [size=8] Region 2: Memory at c0000000 (32-bit, prefetchable) [size=256M] Region 3: Memory at d0180000 (32-bit, non-prefetchable) [size=256K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) Subsystem: Hewlett-Packard Company NX6110/NC6120 Latency: 0 Region 0: Memory at d0200000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- lspci -n 00:00.0 0600: 8086:2590 (rev 03) 00:02.0 0300: 8086:2592 (rev 03) 00:02.1 0380: 8086:2792 (rev 03) 00:1d.0 0c03: 8086:2658 (rev 03) 00:1d.1 0c03: 8086:2659 (rev 03) 00:1d.2 0c03: 8086:265a (rev 03) 00:1d.3 0c03: 8086:265b (rev 03) 00:1d.7 0c03: 8086:265c (rev 03) 00:1e.0 0604: 8086:2448 (rev d3) 00:1e.2 0401: 8086:266e (rev 03) 00:1e.3 0703: 8086:266d (rev 03) 00:1f.0 0601: 8086:2641 (rev 03) 00:1f.1 0101: 8086:266f (rev 03) 02:04.0 0280: 8086:4220 (rev 05) (WW) intel: No matching Device section for instance (BusID PCI:0:2:1) found (--) Chipset 915GM found > Does Xv based video work again if you add > Option "tiling" "false" > to the Intel device section of your xorg.conf? no , seems that not obey to Option "tiling" "false" I try latest git and here is the xorg diff in attach Thanks, > > I thought Wang's fix would have taken care of this problem, but it > sounds like we still have a bug here... > > Jesse > > On Sunday, July 29, 2007 11:29 am Sergio Monteiro Basto wrote: > > Hi , I done a bisect the git xf86-video-intel > > and here is the results: > > -------------- > > drv-intel > > bad vo xv: > > HEAD is now at 04130ac... Fix i915 rendering for tiled buffer > > version 1 > > > > bad vo xv: > > 88f8b688e2316ae4a1f7485f0010ce90de54783a > > HEAD is now at 88f8b68... Fix some physical address handling for >4GB > > addresses > > verison 2 > > > > bad vo xv: > > HEAD is now at 4359df9... Fix tiling and fb compression defaults for > > 965 (not yet fully supported). > > version 5 > > > > bad vo xv: > > HEAD is now at ca593a5... FBC and tiling changes > > version 6 > > > > good: > > 8798ef11321ee6957919279076758d47ad956cf3 > > HEAD is now at 8798ef1... Merge branch 'master' into fbc > > version 4 > > > > good: > > HEAD is now at 8919b22... Re-add tiling kludge, but only for 965 > > version 3 > > > > good: > > 3c552af65d28fafec1d09484a8914b690b961349 > > Update documentation and bump driver version to 2.1.0. > > > > and xorg diff of last good and first bad Xorg.log -- Sérgio M. B. |